| Message ID | 20230928063448.3544464-2-xianwei.zhao@amlogic.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add C3 SoC PLLs and Peripheral clock | expand |
On Thu, 28 Sep 2023 14:34:45 +0800, Xianwei Zhao wrote: > Add the C3 PLL clock controller dt-bindings for Amlogic C3 SoC family > > Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> > --- > .../bindings/clock/amlogic,c3-pll-clkc.yaml | 53 +++++++++++++++++++ > .../dt-bindings/clock/amlogic,c3-pll-clkc.h | 42 +++++++++++++++ > 2 files changed, 95 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml > create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml:2:1: [error] missing document start "---" (document-start) ./Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml:50:1: [error] syntax error: found character '\t' that cannot start any token (syntax) dtschema/dtc warnings/errors: make[2]: *** Deleting file 'Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.example.dts' Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml:4:1: but found another document make[2]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.example.dts] Error 1 make[2]: *** Waiting for unfinished jobs.... ./Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml:4:1: but found another document /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml: ignoring, error parsing file make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1427: dt_binding_check] Error 2 make: *** [Makefile:234: __sub-make] Error 2 doc reference errors (make refcheckdocs): Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml: Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230928063448.3544464-2-xianwei.zhao@amlogic.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
diff --git a/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml new file mode 100644 index 000000000000..18c0eb5ac3e4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic C3 serials PLL Clock Controller + +maintainers: + - Chuan Liu <chuan.liu@amlogic.com> + +properties: + compatible: + const: amlogic,c3-pll-clkc + + reg: + maxItems: 1 + + clocks: + minItems: 2 + items: + - description: input pll_in + - description: input mclk_pll_in + + clock-names: + minItems: 2 + items: + - const: pll_in + - const: mclk_pll_in + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clkc_pll: clock-controller@8000 { + compatible = "amlogic,c3-pll-clkc"; + reg = <0x0 0x8000 0x0 0x1a4>; + clocks = <&clkc_periphs CLKID_PLL_IN>, + <&clkc_periphs CLKID_MCLK_PLL_IN>; + clock-names = "pll_in", "mclk_pll_in"; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/amlogic,c3-pll-clkc.h b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h new file mode 100644 index 000000000000..aa731e8fae29 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu <chuan.liu@amlogic.com> + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H + +#define CLKID_FIXED_PLL_DCO 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV40_DIV 2 +#define CLKID_FCLK_DIV40 3 +#define CLKID_FCLK_DIV2_DIV 4 +#define CLKID_FCLK_DIV2 5 +#define CLKID_FCLK_DIV2P5_DIV 6 +#define CLKID_FCLK_DIV2P5 7 +#define CLKID_FCLK_DIV3_DIV 8 +#define CLKID_FCLK_DIV3 9 +#define CLKID_FCLK_DIV4_DIV 10 +#define CLKID_FCLK_DIV4 11 +#define CLKID_FCLK_DIV5_DIV 12 +#define CLKID_FCLK_DIV5 13 +#define CLKID_FCLK_DIV7_DIV 14 +#define CLKID_FCLK_DIV7 15 +#define CLKID_GP0_PLL_DCO 16 +#define CLKID_GP0_PLL 17 +#define CLKID_HIFI_PLL_DCO 18 +#define CLKID_HIFI_PLL 19 +#define CLKID_MCLK_PLL_DCO 20 +#define CLKID_MCLK_PLL 21 +#define CLKID_MCLK_PLL_CLK 22 +#define CLKID_MCLK0_SEL 23 +#define CLKID_MCLK0_SEL_OUT 24 +#define CLKID_MCLK0_DIV 25 +#define CLKID_MCLK0 26 +#define CLKID_MCLK1_SEL 27 +#define CLKID_MCLK1_SEL_OUT 28 +#define CLKID_MCLK1_DIV 29 +#define CLKID_MCLK1 30 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */
Add the C3 PLL clock controller dt-bindings for Amlogic C3 SoC family Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> --- .../bindings/clock/amlogic,c3-pll-clkc.yaml | 53 +++++++++++++++++++ .../dt-bindings/clock/amlogic,c3-pll-clkc.h | 42 +++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h