| Message ID | 20231004123458.2251635-1-festevam@gmail.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [RESEND,v4] clk: imx: imx6sx: Allow a different LCDIF1 clock parent | expand |
On 23-10-04 09:34:58, Fabio Estevam wrote: > From: Fabio Estevam <festevam@denx.de> > > It is not a good idea to hardcode the LCDIF1 parent inside the > clock driver because some users may want to use a different clock > parent for LCDIF1. One of the reasons could be related to EMI tests. > > Remove the harcoded LCDIF1 parent when the LCDIF1 parent is described > via devicetree. > > Old dtb's that do not describe the LCDIF1 parent via devicetree will > use the same PLL5 clock as parent to keep the original behavior. > > Signed-off-by: Fabio Estevam <festevam@denx.de> > Reviewed-by: Abel Vesa <abel.vesa@linaro.org> I applied already the first v4 you sent. https://lore.kernel.org/all/169642294508.713950.12324349089481800725.b4-ty@linaro.org/ Thanks. > --- > Changes since v3: > - Check for the presence of 'assigned-clock-parents'. (Stephen) > > drivers/clk/imx/clk-imx6sx.c | 14 +++++++++++--- > 1 file changed, 11 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c > index 3f1502933e59..69f8f6f9ca49 100644 > --- a/drivers/clk/imx/clk-imx6sx.c > +++ b/drivers/clk/imx/clk-imx6sx.c > @@ -121,6 +121,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) > { > struct device_node *np; > void __iomem *base; > + bool lcdif1_assigned_clk; > > clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, > IMX6SX_CLK_CLK_END), GFP_KERNEL); > @@ -498,9 +499,16 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) > clk_set_parent(hws[IMX6SX_CLK_EIM_SLOW_SEL]->clk, hws[IMX6SX_CLK_PLL2_PFD2]->clk); > clk_set_rate(hws[IMX6SX_CLK_EIM_SLOW]->clk, 132000000); > > - /* set parent clock for LCDIF1 pixel clock */ > - clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk, hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk); > - clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk, hws[IMX6SX_CLK_LCDIF1_PODF]->clk); > + np = of_find_node_by_path("/soc/bus@2200000/spba-bus@2240000/lcdif@2220000"); > + lcdif1_assigned_clk = of_find_property(np, "assigned-clock-parents", NULL); > + > + /* Set parent clock for LCDIF1 pixel clock if not done via devicetree */ > + if (!lcdif1_assigned_clk) { > + clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk, > + hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk); > + clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk, > + hws[IMX6SX_CLK_LCDIF1_PODF]->clk); > + } > > /* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */ > if (clk_set_parent(hws[IMX6SX_CLK_LVDS1_SEL]->clk, hws[IMX6SX_CLK_PCIE_REF_125M]->clk)) > -- > 2.34.1 >
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index 3f1502933e59..69f8f6f9ca49 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -121,6 +121,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; + bool lcdif1_assigned_clk; clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, IMX6SX_CLK_CLK_END), GFP_KERNEL); @@ -498,9 +499,16 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_set_parent(hws[IMX6SX_CLK_EIM_SLOW_SEL]->clk, hws[IMX6SX_CLK_PLL2_PFD2]->clk); clk_set_rate(hws[IMX6SX_CLK_EIM_SLOW]->clk, 132000000); - /* set parent clock for LCDIF1 pixel clock */ - clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk, hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk); - clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk, hws[IMX6SX_CLK_LCDIF1_PODF]->clk); + np = of_find_node_by_path("/soc/bus@2200000/spba-bus@2240000/lcdif@2220000"); + lcdif1_assigned_clk = of_find_property(np, "assigned-clock-parents", NULL); + + /* Set parent clock for LCDIF1 pixel clock if not done via devicetree */ + if (!lcdif1_assigned_clk) { + clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk, + hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk); + clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk, + hws[IMX6SX_CLK_LCDIF1_PODF]->clk); + } /* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */ if (clk_set_parent(hws[IMX6SX_CLK_LVDS1_SEL]->clk, hws[IMX6SX_CLK_PCIE_REF_125M]->clk))