| Message ID | 20231010132701.1658737-5-claudiu.beznea.uj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | arm64: dts: renesas: Add SDHI1 and SDHI2 for RZ/G3S | expand |
Hi Claudiu, Thanks for your patch! On Tue, Oct 10, 2023 at 3:27 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Add SDHI2 to RZ/G3S Smarc SoM. SDHI2 pins are multiplexed with SCIF1, SSI3, SSI0 > IRQ0. The selection b/w SDHI2 and SCIF1, SSI3, IRQ0 is done with a switch and IRQ1 (twice). Or just say "The selection is done ...". > button. To be able to select b/w these a compilation flag has been added > (SW_SD2_EN) at the moment being instantiated to select SDHI2. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi > +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi > @@ -13,14 +13,21 @@ > * @SW_SD0_DEV_SEL: > * 0 - SD0 is connected to eMMC > * 1 - SD0 is connected to uSD0 card > + * @SW_SD2_EN: > + * 0 - SCIF1, SSI3, IRQ0, IRQ1 connected to SoC SSI0 > + * 1 - SD2 is connected to SoC > */ > #define SW_SD0_DEV_SEL 1 > +#define SW_SD2_EN 1 > @@ -100,6 +125,19 @@ &sdhi0 { > }; > #endif > > +#if SW_SD2_EN > +&sdhi2 { > + pinctrl-0 = <&sdhi2_pins>; > + pinctrl-1 = <&sdhi2_pins>; > + pinctrl-names = "default", "state_uhs"; Do you need two states if there is only a single voltage? AFAIK, UHS needs 1.8V. > + vmmc-supply = <&vcc_sdhi2>; > + vqmmc-supply = <®_3p3v>; > + bus-width = <4>; > + max-frequency = <50000000>; > + status = "okay"; > +}; > +#endif > + > &pinctrl { > sdhi0_pins: sd0 { > data { Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi, Geert, Thanks for reviewing! On 12.10.2023 17:36, Geert Uytterhoeven wrote: > Hi Claudiu, > > Thanks for your patch! > > On Tue, Oct 10, 2023 at 3:27 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> >> Add SDHI2 to RZ/G3S Smarc SoM. SDHI2 pins are multiplexed with SCIF1, SSI3, > > SSI0 > >> IRQ0. The selection b/w SDHI2 and SCIF1, SSI3, IRQ0 is done with a switch > > and IRQ1 (twice). Or just say "The selection is done ...". > >> button. To be able to select b/w these a compilation flag has been added >> (SW_SD2_EN) at the moment being instantiated to select SDHI2. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > >> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi >> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi >> @@ -13,14 +13,21 @@ >> * @SW_SD0_DEV_SEL: >> * 0 - SD0 is connected to eMMC >> * 1 - SD0 is connected to uSD0 card >> + * @SW_SD2_EN: >> + * 0 - SCIF1, SSI3, IRQ0, IRQ1 connected to SoC > > SSI0 > >> + * 1 - SD2 is connected to SoC >> */ >> #define SW_SD0_DEV_SEL 1 >> +#define SW_SD2_EN 1 > >> @@ -100,6 +125,19 @@ &sdhi0 { >> }; >> #endif >> >> +#if SW_SD2_EN >> +&sdhi2 { >> + pinctrl-0 = <&sdhi2_pins>; >> + pinctrl-1 = <&sdhi2_pins>; >> + pinctrl-names = "default", "state_uhs"; > > Do you need two states if there is only a single voltage? > AFAIK, UHS needs 1.8V. I had the impression that driver needs them both anyway. I double checked now and it seems it is not the case. I'll update it in the next version. Thank you, Claudiu Beznea > >> + vmmc-supply = <&vcc_sdhi2>; >> + vqmmc-supply = <®_3p3v>; >> + bus-width = <4>; >> + max-frequency = <50000000>; >> + status = "okay"; >> +}; >> +#endif >> + >> &pinctrl { >> sdhi0_pins: sd0 { >> data { > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 185ca8289a35..58a68356b9d7 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -13,14 +13,21 @@ * @SW_SD0_DEV_SEL: * 0 - SD0 is connected to eMMC * 1 - SD0 is connected to uSD0 card + * @SW_SD2_EN: + * 0 - SCIF1, SSI3, IRQ0, IRQ1 connected to SoC + * 1 - SD2 is connected to SoC */ #define SW_SD0_DEV_SEL 1 +#define SW_SD2_EN 1 / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; aliases { mmc0 = &sdhi0; +#if SW_SD2_EN + mmc2 = &sdhi2; +#endif }; chosen { @@ -63,6 +70,24 @@ reg_1p8v: regulator1 { regulator-always-on; }; #endif + + vcc_sdhi2: regulator2 { + compatible = "regulator-fixed"; + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_3p3v: regulator3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &extal_clk { @@ -100,6 +125,19 @@ &sdhi0 { }; #endif +#if SW_SD2_EN +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&vcc_sdhi2>; + vqmmc-supply = <®_3p3v>; + bus-width = <4>; + max-frequency = <50000000>; + status = "okay"; +}; +#endif + &pinctrl { sdhi0_pins: sd0 { data { @@ -139,4 +177,26 @@ sdhi0_emmc_pins: sd0-emmc { "SD0_CLK", "SD0_CMD", "SD0_RST#"; power-source = <1800>; }; + + sdhi2_pins: sd2 { + data { + pins = "P11_2", "P11_3", "P12_0", "P12_1"; + input-enable; + }; + + ctrl { + pins = "P11_1"; + input-enable; + }; + + mux { + pinmux = <RZG2L_PORT_PINMUX(11, 0, 8)>, /* SD2_CLK */ + <RZG2L_PORT_PINMUX(11, 1, 8)>, /* SD2_CMD */ + <RZG2L_PORT_PINMUX(11, 2, 8)>, /* SD2_DATA0 */ + <RZG2L_PORT_PINMUX(11, 3, 8)>, /* SD2_DATA1 */ + <RZG2L_PORT_PINMUX(12, 0, 8)>, /* SD2_DATA2 */ + <RZG2L_PORT_PINMUX(12, 1, 8)>, /* SD2_DATA3 */ + <RZG2L_PORT_PINMUX(14, 1, 7)>; /* SD2_CD# */ + }; + }; };