diff mbox series

[2/8] dt-bindings: clock: ipq5332: drop the few nss clocks definition

Message ID 20231030-ipq5332-nsscc-v1-2-6162a2c65f0a@quicinc.com (mailing list archive)
State Changes Requested, archived
Headers show
Series Add NSS clock controller support for IPQ5332 | expand

Commit Message

Kathiravan Thirumoorthy Oct. 30, 2023, 9:47 a.m. UTC
gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk, gcc_nssnoc_nsscc_clk are
enabled by default and it's RCG is properly configured by bootloader.

Some of the NSS clocks needs these clocks to be enabled. To avoid
these clocks being disabled by clock framework, drop these entries.

Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
 include/dt-bindings/clock/qcom,ipq5332-gcc.h | 3 ---
 1 file changed, 3 deletions(-)

Comments

Krzysztof Kozlowski Oct. 30, 2023, 11:07 a.m. UTC | #1
On 30/10/2023 10:47, Kathiravan Thirumoorthy wrote:
> gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk, gcc_nssnoc_nsscc_clk are
> enabled by default and it's RCG is properly configured by bootloader.
> 
> Some of the NSS clocks needs these clocks to be enabled. To avoid
> these clocks being disabled by clock framework, drop these entries.

This is not the way to prevent Linux from disabling the clocks. The way
is to mark them as critical, so I do not think you provided accurate
rationale for bindings change.

Best regards,
Krzysztof
Stephen Boyd Oct. 30, 2023, 6:56 p.m. UTC | #2
Quoting Kathiravan Thirumoorthy (2023-10-30 02:47:17)
> gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk, gcc_nssnoc_nsscc_clk are
> enabled by default and it's RCG is properly configured by bootloader.
> 
> Some of the NSS clocks needs these clocks to be enabled. To avoid
> these clocks being disabled by clock framework, drop these entries.
> 
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---

Instead of this patch just drop the clks from the table and enable the
clks during probe with register writes.
Kathiravan Thirumoorthy Oct. 31, 2023, 4:20 a.m. UTC | #3
On 10/31/2023 12:26 AM, Stephen Boyd wrote:
> Quoting Kathiravan Thirumoorthy (2023-10-30 02:47:17)
>> gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk, gcc_nssnoc_nsscc_clk are
>> enabled by default and it's RCG is properly configured by bootloader.
>>
>> Some of the NSS clocks needs these clocks to be enabled. To avoid
>> these clocks being disabled by clock framework, drop these entries.
>>
>> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
>> ---
> 
> Instead of this patch just drop the clks from the table and enable the
> clks during probe with register writes.


Thanks for the suggestion Stephen, will handle this way in V2. Between, 
I think still the entries in the dt-bindings can be dropped along with 
the entries in the clock table?
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
index 8a405a0a96d0..4649026da332 100644
--- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
@@ -55,7 +55,6 @@ 
 #define GCC_NSSCC_CLK					46
 #define GCC_NSSCFG_CLK					47
 #define GCC_NSSNOC_ATB_CLK				48
-#define GCC_NSSNOC_NSSCC_CLK				49
 #define GCC_NSSNOC_QOSGEN_REF_CLK			50
 #define GCC_NSSNOC_SNOC_1_CLK				51
 #define GCC_NSSNOC_SNOC_CLK				52
@@ -124,8 +123,6 @@ 
 #define GCC_SDCC1_APPS_CLK_SRC				115
 #define GCC_SLEEP_CLK_SRC				116
 #define GCC_SNOC_LPASS_CFG_CLK				117
-#define GCC_SNOC_NSSNOC_1_CLK				118
-#define GCC_SNOC_NSSNOC_CLK				119
 #define GCC_SNOC_PCIE3_1LANE_1_M_CLK			120
 #define GCC_SNOC_PCIE3_1LANE_1_S_CLK			121
 #define GCC_SNOC_PCIE3_1LANE_M_CLK			122