| Message ID | 20231111160806.32954-4-marek.vasut+renesas@mailbox.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [v2,1/4] dt-bindings: clk: rs9: Add 9FGV0841 | expand |
Hi Marek Vasut, Thanks for the patch. > Subject: [PATCH v2 4/4] clk: rs9: Add support for 9FGV0841 > > This model is similar to 9FGV0441, the DIFx bits start at bit 0 again, > except this chip has 8 outputs. > > Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Cheers, Biju > --- > Cc: Alexander Stein <alexander.stein@ew.tq-group.com> > Cc: Conor Dooley <conor+dt@kernel.org> > Cc: Geert Uytterhoeven <geert+renesas@glider.be> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Stephen Boyd <sboyd@kernel.org> > Cc: devicetree@vger.kernel.org > Cc: linux-clk@vger.kernel.org > Cc: linux-renesas-soc@vger.kernel.org > --- > V2: Update on top of 2/4 and 3/4 > --- > drivers/clk/clk-renesas-pcie.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas- > pcie.c index 5064016afbc3..6d494e5f8fa7 100644 > --- a/drivers/clk/clk-renesas-pcie.c > +++ b/drivers/clk/clk-renesas-pcie.c > @@ -7,6 +7,7 @@ > * Currently supported: > * - 9FGV0241 > * - 9FGV0441 > + * - 9FGV0841 > * > * Copyright (C) 2022 Marek Vasut <marex@denx.de> > */ > @@ -54,6 +55,7 @@ > enum rs9_model { > RENESAS_9FGV0241, > RENESAS_9FGV0441, > + RENESAS_9FGV0841, > }; > > /* Structure to describe features of a particular 9-series model */ @@ - > 391,9 +393,16 @@ static const struct rs9_chip_info renesas_9fgv0441_info = > { > .did = RS9_REG_DID_TYPE_FGV | 0x04, > }; > > +static const struct rs9_chip_info renesas_9fgv0841_info = { > + .num_clks = 8, > + .outshift = 0, > + .did = RS9_REG_DID_TYPE_FGV | 0x08, > +}; > + > static const struct i2c_device_id rs9_id[] = { > { "9fgv0241", .driver_data = > (kernel_ulong_t)&renesas_9fgv0241_info }, > { "9fgv0441", .driver_data = > (kernel_ulong_t)&renesas_9fgv0441_info }, > + { "9fgv0841", .driver_data = > (kernel_ulong_t)&renesas_9fgv0841_info }, > { } > }; > MODULE_DEVICE_TABLE(i2c, rs9_id); > @@ -401,6 +410,7 @@ MODULE_DEVICE_TABLE(i2c, rs9_id); static const struct > of_device_id clk_rs9_of_match[] = { > { .compatible = "renesas,9fgv0241", .data = > &renesas_9fgv0241_info }, > { .compatible = "renesas,9fgv0441", .data = > &renesas_9fgv0441_info }, > + { .compatible = "renesas,9fgv0841", .data = > &renesas_9fgv0841_info }, > { } > }; > MODULE_DEVICE_TABLE(of, clk_rs9_of_match); > -- > 2.42.0
diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c index 5064016afbc3..6d494e5f8fa7 100644 --- a/drivers/clk/clk-renesas-pcie.c +++ b/drivers/clk/clk-renesas-pcie.c @@ -7,6 +7,7 @@ * Currently supported: * - 9FGV0241 * - 9FGV0441 + * - 9FGV0841 * * Copyright (C) 2022 Marek Vasut <marex@denx.de> */ @@ -54,6 +55,7 @@ enum rs9_model { RENESAS_9FGV0241, RENESAS_9FGV0441, + RENESAS_9FGV0841, }; /* Structure to describe features of a particular 9-series model */ @@ -391,9 +393,16 @@ static const struct rs9_chip_info renesas_9fgv0441_info = { .did = RS9_REG_DID_TYPE_FGV | 0x04, }; +static const struct rs9_chip_info renesas_9fgv0841_info = { + .num_clks = 8, + .outshift = 0, + .did = RS9_REG_DID_TYPE_FGV | 0x08, +}; + static const struct i2c_device_id rs9_id[] = { { "9fgv0241", .driver_data = (kernel_ulong_t)&renesas_9fgv0241_info }, { "9fgv0441", .driver_data = (kernel_ulong_t)&renesas_9fgv0441_info }, + { "9fgv0841", .driver_data = (kernel_ulong_t)&renesas_9fgv0841_info }, { } }; MODULE_DEVICE_TABLE(i2c, rs9_id); @@ -401,6 +410,7 @@ MODULE_DEVICE_TABLE(i2c, rs9_id); static const struct of_device_id clk_rs9_of_match[] = { { .compatible = "renesas,9fgv0241", .data = &renesas_9fgv0241_info }, { .compatible = "renesas,9fgv0441", .data = &renesas_9fgv0441_info }, + { .compatible = "renesas,9fgv0841", .data = &renesas_9fgv0841_info }, { } }; MODULE_DEVICE_TABLE(of, clk_rs9_of_match);
This model is similar to 9FGV0441, the DIFx bits start at bit 0 again, except this chip has 8 outputs. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> --- Cc: Alexander Stein <alexander.stein@ew.tq-group.com> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: Update on top of 2/4 and 3/4 --- drivers/clk/clk-renesas-pcie.c | 10 ++++++++++ 1 file changed, 10 insertions(+)