diff mbox series

[3/3] clk: meson: g12a: add CSI & ISP gates clocks

Message ID 20231114-topic-amlogic-upstream-isp-clocks-v1-3-223958791501@linaro.org (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series clk: meson: add MIPI ISP & CSI PHY clocks | expand

Commit Message

Neil Armstrong Nov. 14, 2023, 10:14 a.m. UTC
Add the gates entires for the CSI ISP domain and CSI PHYs.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 drivers/clk/meson/g12a.c | 9 +++++++++
 1 file changed, 9 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index a8312f29d1cc..b0bd37ae1a81 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -4274,9 +4274,12 @@  static MESON_GATE(g12a_htx_hdcp22,		HHI_GCLK_MPEG2,	3);
 static MESON_GATE(g12a_htx_pclk,		HHI_GCLK_MPEG2,	4);
 static MESON_GATE(g12a_bt656,			HHI_GCLK_MPEG2,	6);
 static MESON_GATE(g12a_usb1_to_ddr,		HHI_GCLK_MPEG2,	8);
+static MESON_GATE(g12b_mipi_isp_gate,		HHI_GCLK_MPEG2,	17);
 static MESON_GATE(g12a_mmc_pclk,		HHI_GCLK_MPEG2,	11);
 static MESON_GATE(g12a_uart2,			HHI_GCLK_MPEG2,	15);
 static MESON_GATE(g12a_vpu_intr,		HHI_GCLK_MPEG2,	25);
+static MESON_GATE(g12b_csi_phy1,		HHI_GCLK_MPEG2,	28);
+static MESON_GATE(g12b_csi_phy0,		HHI_GCLK_MPEG2,	29);
 static MESON_GATE(g12a_gic,			HHI_GCLK_MPEG2,	30);
 
 static MESON_GATE(g12a_vclk2_venci0,		HHI_GCLK_OTHER,	1);
@@ -4792,6 +4795,9 @@  static struct clk_hw *g12b_hw_clks[] = {
 	[CLKID_MIPI_ISP_SEL]		= &g12b_mipi_isp_sel.hw,
 	[CLKID_MIPI_ISP_DIV]		= &g12b_mipi_isp_div.hw,
 	[CLKID_MIPI_ISP]		= &g12b_mipi_isp.hw,
+	[CLKID_MIPI_ISP_GATE]		= &g12b_mipi_isp_gate.hw,
+	[CLKID_MIPI_ISP_CSI_PHY0]	= &g12b_csi_phy0.hw,
+	[CLKID_MIPI_ISP_CSI_PHY1]	= &g12b_csi_phy1.hw,
 };
 
 static struct clk_hw *sm1_hw_clks[] = {
@@ -5287,6 +5293,9 @@  static struct clk_regmap *const g12a_clk_regmaps[] = {
 	&g12b_mipi_isp_sel,
 	&g12b_mipi_isp_div,
 	&g12b_mipi_isp,
+	&g12b_mipi_isp_gate,
+	&g12b_csi_phy1,
+	&g12b_csi_phy0,
 };
 
 static const struct reg_sequence g12a_init_regs[] = {