Message ID | 20240122-envoy-chosen-7ae961b3b07e@spud (mailing list archive) |
---|---|
State | Awaiting Upstream, archived |
Headers | show |
Series | MPFS clock fixes required for correct CAN clock modeling | expand |
diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h index 79775a5134ca..b52f19a2b480 100644 --- a/include/dt-bindings/clock/microchip,mpfs-clock.h +++ b/include/dt-bindings/clock/microchip,mpfs-clock.h @@ -44,6 +44,11 @@ #define CLK_RTCREF 33 #define CLK_MSSPLL 34 +#define CLK_MSSPLL0 34 +#define CLK_MSSPLL1 35 +#define CLK_MSSPLL2 36 +#define CLK_MSSPLL3 37 +/* 38 is reserved for MSS PLL internals */ /* Clock Conditioning Circuitry Clock IDs */