diff mbox series

[v4,4/8] clk: qcom: ipq5332: add gpll0_out_aux clock

Message ID 20240122-ipq5332-nsscc-v4-4-19fa30019770@quicinc.com (mailing list archive)
State Changes Requested, archived
Headers show
Series Add NSS clock controller support for Qualcomm IPQ5332 | expand

Commit Message

Kathiravan Thirumoorthy Jan. 22, 2024, 5:57 a.m. UTC 
Add support for gpll0_out_aux clock which acts as the parent for
certain networking subsystem (NSS) clocks.

Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
 drivers/clk/qcom/gcc-ipq5332.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

Comments

Andrew Lunn Jan. 25, 2024, 8:11 p.m. UTC | #1 
On Mon, Jan 22, 2024 at 11:27:00AM +0530, Kathiravan Thirumoorthy wrote:
> Add support for gpll0_out_aux clock which acts as the parent for
> certain networking subsystem (NSS) clocks.

This answers the question i asked for the previous patch.

Why did you split this into two patches?

Please also give a more detailed description, rather than the vague
'certain networking subsystem (NSS) clocks'

If you device tree and drivers are correct, i should be able to work
out what the clock tree looks like, so there is no point trying to
hide the information.

     Andrew
Kathiravan Thirumoorthy Feb. 14, 2024, 9:28 a.m. UTC | #2 
On 1/26/2024 1:41 AM, Andrew Lunn wrote:
> On Mon, Jan 22, 2024 at 11:27:00AM +0530, Kathiravan Thirumoorthy wrote:
>> Add support for gpll0_out_aux clock which acts as the parent for
>> certain networking subsystem (NSS) clocks.
> 
> This answers the question i asked for the previous patch.
> 
> Why did you split this into two patches?


driver and binding patch should be separate patches, else checkpatch 
will complain it.

> 
> Please also give a more detailed description, rather than the vague
> 'certain networking subsystem (NSS) clocks'


Sure, will call out the clock names explicitly in the next spin.

> 
> If you device tree and drivers are correct, i should be able to work
> out what the clock tree looks like, so there is no point trying to
> hide the information.


Clocks which are part of the NSSCC are used by the Networking drivers 
which are in the pipeline for upstream. Once the networking patches are 
submitted in the list, we should be able to get the clear picture of the 
clock tree.


> 
>       Andrew
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index 38a570b68813..9a5f0c98f734 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -87,6 +87,19 @@  static struct clk_alpha_pll_postdiv gpll0 = {
 	},
 };
 
+static struct clk_alpha_pll_postdiv gpll0_out_aux = {
+	.offset = 0x20000,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
+	.width = 4,
+	.clkr.hw.init = &(const struct clk_init_data) {
+		.name = "gpll0_out_aux",
+		.parent_hws = (const struct clk_hw *[]) {
+				&gpll0_main.clkr.hw },
+		.num_parents = 1,
+		.ops = &clk_alpha_pll_postdiv_ro_ops,
+	},
+};
+
 static struct clk_alpha_pll gpll2_main = {
 	.offset = 0x21000,
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
@@ -3393,6 +3406,7 @@  static struct clk_regmap *gcc_ipq5332_clocks[] = {
 	[GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr,
 	[GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr,
 	[GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr,
+	[GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq5332_resets[] = {