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Mon, 22 Jan 2024 05:57:47 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sun, 21 Jan 2024 21:57:41 -0800 From: Kathiravan Thirumoorthy Date: Mon, 22 Jan 2024 11:27:03 +0530 Subject: [PATCH v4 7/8] arm64: dts: qcom: ipq5332: add support for the NSSCC Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240122-ipq5332-nsscc-v4-7-19fa30019770@quicinc.com> References: <20240122-ipq5332-nsscc-v4-0-19fa30019770@quicinc.com> In-Reply-To: <20240122-ipq5332-nsscc-v4-0-19fa30019770@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Richard Cochran , "Catalin Marinas" , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; 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Signed-off-by: Kathiravan Thirumoorthy --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 42e2e48b2bc3..1e280e045b00 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -15,6 +15,18 @@ / { #size-cells = <2>; clocks { + cmn_pll_nss_200m_clk: cmn-pll-nss-200m-clk { + compatible = "fixed-clock"; + clock-frequency = <200000000>; + #clock-cells = <0>; + }; + + cmn_pll_nss_300m_clk: cmn-pll-nss-300m-clk { + compatible = "fixed-clock"; + clock-frequency = <300000000>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -473,6 +485,22 @@ frame@b128000 { status = "disabled"; }; }; + + nsscc: clock-controller@39b00000 { + compatible = "qcom,ipq5332-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&cmn_pll_nss_200m_clk>, + <&cmn_pll_nss_300m_clk>, + <&gcc GPLL0_OUT_AUX>, + <0>, + <0>, + <0>, + <0>, + <&xo_board>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; }; timer {