From patchwork Tue Jan 23 02:56:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhifeng Tang X-Patchwork-Id: 13526800 Received: from SHSQR01.spreadtrum.com (unknown [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC311812 for ; Tue, 23 Jan 2024 02:56:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=222.66.158.135 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705978597; cv=none; b=dmtTByEBPo+udrzpH4A803V03MD8nt00NgkkmOYSRReMOir0QurDYpAACpxtThpSzifiCCLu9cw/MByEGbrgNNiMtptCf/lHVNo8XVRHxSKgliowiIkpEMI1Uhfp3gzn5TZtRvaoRlHu/6KINMb9EBSp5oorbxEaXieTQEzjs8I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705978597; c=relaxed/simple; bh=HO+P9HHk5xdN8+9NMbhUtb2fAk3bvYT5z8UnLdpzVaE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mgLxb/0JQIHGv44EsD5/TAfFB85mTaeB2dDuObq/QUhZ6zooELpyLuy1+U4CLLLun6tLPD8Drm1DjJCee8jKnB5t+PmdpL48smycv7PRWbawXjn2zGOuFuOO3zj8P9Zpky8F+krvunyYphFrxFFLDfwRedX2q8LBEGUXfFYDzVE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com; spf=pass smtp.mailfrom=unisoc.com; arc=none smtp.client-ip=222.66.158.135 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 40N2uJox022812; Tue, 23 Jan 2024 10:56:19 +0800 (+08) (envelope-from zhifeng.tang@unisoc.com) Received: from SHDLP.spreadtrum.com (shmbx04.spreadtrum.com [10.0.1.214]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4TJs3t5pckz2S82tk; Tue, 23 Jan 2024 10:48:58 +0800 (CST) Received: from xm9614pcu.spreadtrum.com (10.13.2.29) by shmbx04.spreadtrum.com (10.0.1.214) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Tue, 23 Jan 2024 10:56:18 +0800 From: Zhifeng Tang To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Orson Zhai , Baolin Wang , Chunyan Zhang , Philipp Zabel CC: , , , Zhifeng Tang , Wenming Wu Subject: [PATCH V4 3/3] arm64: dts: sprd: Add reset controller driver for UMS512 Date: Tue, 23 Jan 2024 10:56:13 +0800 Message-ID: <20240123025613.3976-4-zhifeng.tang@unisoc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240123025613.3976-1-zhifeng.tang@unisoc.com> References: <20240123025613.3976-1-zhifeng.tang@unisoc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHCAS01.spreadtrum.com (10.0.1.201) To shmbx04.spreadtrum.com (10.0.1.214) X-MAIL: SHSQR01.spreadtrum.com 40N2uJox022812 From: "zhifeng.tang" In most of Sprd SOCs,The clock controller register block also contains reset bits for some of these peripherals,so reset controller and clock provider are combined together as a block, and put it under the driver/clk/. Signed-off-by: zhifeng.tang --- arch/arm64/boot/dts/sprd/ums512.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/sprd/ums512.dtsi b/arch/arm64/boot/dts/sprd/ums512.dtsi index 024be594c47d..08d0adf6624c 100644 --- a/arch/arm64/boot/dts/sprd/ums512.dtsi +++ b/arch/arm64/boot/dts/sprd/ums512.dtsi @@ -7,6 +7,7 @@ #include #include +#include / { interrupt-parent = <&gic>; @@ -182,6 +183,7 @@ clocks = <&ext_26m>; clock-names = "ext-26m"; #clock-cells = <1>; + #reset-cells = <1>; }; }; @@ -316,6 +318,7 @@ clocks = <&ext_26m>; clock-names = "ext-26m"; #clock-cells = <1>; + #reset-cells = <1>; }; }; @@ -333,6 +336,7 @@ clocks = <&ext_26m>; clock-names = "ext-26m"; #clock-cells = <1>; + #reset-cells = <1>; }; }; @@ -348,6 +352,7 @@ compatible = "sprd,ums512-audcpapb-gate"; reg = <0x0 0x300>; #clock-cells = <1>; + #reset-cells = <1>; }; }; @@ -363,6 +368,7 @@ compatible = "sprd,ums512-audcpahb-gate"; reg = <0x0 0x300>; #clock-cells = <1>; + #reset-cells = <1>; }; }; @@ -380,6 +386,7 @@ clock-names = "ext-26m"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; }; }; @@ -401,6 +408,7 @@ compatible = "sprd,ums512-mm-gate-clk"; reg = <0x0 0x3000>; #clock-cells = <1>; + #reset-cells = <1>; }; }; @@ -416,6 +424,7 @@ compatible = "sprd,ums512-apapb-gate"; reg = <0x0 0x3000>; #clock-cells = <1>; + #reset-cells = <1>; }; };