| Message ID | 20240130093812.1746512-5-andre.draszik@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | gs101 oriole: peripheral block 0 (peric0) fixes | expand |
On Tue, 30 Jan 2024 09:36:43 +0000, André Draszik wrote: > Wrong pclk clocks have been used in this usi_uart instance here. For > USI and UART, we need the ipclk and pclk, where pclk is the bus clock. > Without it, nothing can work. > > It is unclear what exactly is using USI0_UART_CLK, but it is not > required for the IP to be operational at this stage, while pclk is. > This also brings the DT in line with the clock names expected by the > usi and uart drivers. > > [...] Applied, thanks! [4/6] arm64: dts: exynos: gs101: use correct clocks for usi_uart https://git.kernel.org/krzk/linux/c/21e4e8807bfc7acc0fc9fe3ab69e1dc0662e7ce4 Best regards,
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index e5b665be2d62..f93e937d2726 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -410,7 +410,7 @@ usi_uart: usi@10a000c0 { ranges; #address-cells = <1>; #size-cells = <1>; - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1020>; @@ -422,7 +422,7 @@ serial_0: serial@10a00000 { reg = <0x10a00000 0xc0>; interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>;
Wrong pclk clocks have been used in this usi_uart instance here. For USI and UART, we need the ipclk and pclk, where pclk is the bus clock. Without it, nothing can work. It is unclear what exactly is using USI0_UART_CLK, but it is not required for the IP to be operational at this stage, while pclk is. This also brings the DT in line with the clock names expected by the usi and uart drivers. Update the DTSI accordingly. Fixes: d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Tested-by: Tudor Ambarus <tudor.ambarus@linaro.org> --- v2: * fix a typo in and add an empty line to the commit message * collect Reviewed-by: Tested-by: tags --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)