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AJvYcCX5a8VTWpV4sFSa5fYujLjy8ndXaFZibL3bczmiui6k3aSpS+SZbXeymiHNSfxWE+RH26c8Pu/liarJUvFmBbOcDgNLbUZJRfdd X-Gm-Message-State: AOJu0YwWprvLlB2Yt2qTX8i5W/AofT3UNUf4ypHxiLEHEIpeeorjZzYB b7hCGcGMMWu2zQZ3DTxk0Q6CRdDYnm+p1C8ldpqn3dFCp7oDQN4Xj7FdOa9v5WI= X-Google-Smtp-Source: AGHT+IG+ne10+UGzrxsIM3qTjARf9KX9TPUBRYEZ1G+65MMHUS0yyLw6vNMSFgUqvmX17ex/zLMMnw== X-Received: by 2002:a05:6808:3193:b0:3bf:f4b2:2164 with SMTP id cd19-20020a056808319300b003bff4b22164mr7924507oib.28.1708122779339; Fri, 16 Feb 2024 14:32:59 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id cr3-20020a056808368300b003bff074dd43sm126449oib.58.2024.02.16.14.32.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 14:32:59 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi Cc: Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Tomasz Figa , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 16/16] arm64: dts: exynos: Add CPU clocks Date: Fri, 16 Feb 2024 16:32:45 -0600 Message-Id: <20240216223245.12273-17-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240216223245.12273-1-semen.protsenko@linaro.org> References: <20240216223245.12273-1-semen.protsenko@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Define CPU cluster 0 and CPU cluster 1 CMUs, which generate CPU clocks, and add corresponding CPU clocks to CPU nodes. Signed-off-by: Sam Protsenko --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index 2ba67c3d0681..0706c8534ceb 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -93,6 +93,8 @@ cpu0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0x0>; enable-method = "psci"; + clocks = <&cmu_cpucl0 CLK_CLUSTER0_SCLK>; + clock-names = "cluster0_clk"; }; cpu1: cpu@1 { device_type = "cpu"; @@ -117,6 +119,8 @@ cpu4: cpu@100 { compatible = "arm,cortex-a55"; reg = <0x100>; enable-method = "psci"; + clocks = <&cmu_cpucl1 CLK_CLUSTER1_SCLK>; + clock-names = "cluster1_clk"; }; cpu5: cpu@101 { device_type = "cpu"; @@ -254,6 +258,28 @@ cmu_peri: clock-controller@10030000 { "dout_peri_uart", "dout_peri_ip"; }; + cmu_cpucl1: clock-controller@10800000 { + compatible = "samsung,exynos850-cmu-cpucl1"; + reg = <0x10800000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL1_SWITCH>, + <&cmu_top CLK_DOUT_CPUCL1_DBG>; + clock-names = "oscclk", "dout_cpucl1_switch", + "dout_cpucl1_dbg"; + }; + + cmu_cpucl0: clock-controller@10900000 { + compatible = "samsung,exynos850-cmu-cpucl0"; + reg = <0x10900000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL0_SWITCH>, + <&cmu_top CLK_DOUT_CPUCL0_DBG>; + clock-names = "oscclk", "dout_cpucl0_switch", + "dout_cpucl0_dbg"; + }; + cmu_g3d: clock-controller@11400000 { compatible = "samsung,exynos850-cmu-g3d"; reg = <0x11400000 0x8000>;