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AJvYcCUOL0BKhUi61XaXpBUCVftRBf5m445Sju64zM7DYrHutb2DN7ObnCAC6Mug8oHcHFhmaiWWrG+ZhWCVla7gWeJlWgItKde4i5iW X-Gm-Message-State: AOJu0Yw+0xSnE7/04u/0HNRWvdwQjqDYi6Cb3RX0x8SIYKbYzNUxk52V 5b12yFSnlvOOEJJOSSnRh4z1HoP3UNxFpDHJ8cgByJQp53GvvzO2EzMw31NaHoo09IXoGTvTVaa b X-Google-Smtp-Source: AGHT+IG5usWWuC05SJ1LiQq1mXPRGdfpc9cnTnEuYnyX99oRrWX3v74t1yyKDMb8eWaqJE3G7KVCPQ== X-Received: by 2002:a05:6830:1158:b0:6e4:31e7:c158 with SMTP id x24-20020a056830115800b006e431e7c158mr4959777otq.19.1708122768363; Fri, 16 Feb 2024 14:32:48 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id e24-20020a9d63d8000000b006e2e95e852csm140473otl.3.2024.02.16.14.32.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 14:32:47 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi Cc: Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Tomasz Figa , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/16] clk: samsung: Pull struct exynos_cpuclk into clk-cpu.c Date: Fri, 16 Feb 2024 16:32:32 -0600 Message-Id: <20240216223245.12273-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240216223245.12273-1-semen.protsenko@linaro.org> References: <20240216223245.12273-1-semen.protsenko@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Reduce the scope of struct exynos_cpuclk, as it's only used in clk-cpu.c internally. All drivers using clk-pll.h already include clk.h as well, so this change doesn't break anything. No functional change. Signed-off-by: Sam Protsenko --- drivers/clk/samsung/clk-cpu.c | 29 +++++++++++++++++++++++++ drivers/clk/samsung/clk-cpu.h | 41 +++++------------------------------ 2 files changed, 35 insertions(+), 35 deletions(-) diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index e02730776aaa..6412fd2580e0 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -34,6 +34,8 @@ #include #include #include + +#include "clk.h" #include "clk-cpu.h" #define E4210_SRC_CPU 0x0 @@ -64,6 +66,33 @@ #define DIV_MASK_ALL GENMASK(31, 0) #define MUX_MASK GENMASK(2, 0) +/** + * struct exynos_cpuclk - information about clock supplied to a CPU core + * @hw: handle between CCF and CPU clock + * @alt_parent: alternate parent clock to use when switching the speed + * of the primary parent clock + * @ctrl_base: base address of the clock controller + * @lock: cpu clock domain register access lock + * @cfg: cpu clock rate configuration data + * @num_cfgs: number of array elements in @cfg array + * @clk_nb: clock notifier registered for changes in clock speed of the + * primary parent clock + * @flags: configuration flags for the CPU clock + * + * This structure holds information required for programming the CPU clock for + * various clock speeds. + */ +struct exynos_cpuclk { + struct clk_hw hw; + const struct clk_hw *alt_parent; + void __iomem *ctrl_base; + spinlock_t *lock; + const struct exynos_cpuclk_cfg_data *cfg; + const unsigned long num_cfgs; + struct notifier_block clk_nb; + unsigned long flags; +}; + /* * Helper function to wait until divider(s) have stabilized after the divider * value has changed. diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index 0164bd9ad021..ee57f3638fed 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -8,7 +8,12 @@ #ifndef __SAMSUNG_CLK_CPU_H #define __SAMSUNG_CLK_CPU_H -#include "clk.h" +/* The CPU clock registers have DIV1 configuration register */ +#define CLK_CPU_HAS_DIV1 BIT(0) +/* When ALT parent is active, debug clocks need safe divider values */ +#define CLK_CPU_NEEDS_DEBUG_ALT_DIV BIT(1) +/* The CPU clock registers have Exynos5433-compatible layout */ +#define CLK_CPU_HAS_E5433_REGS_LAYOUT BIT(2) /** * struct exynos_cpuclk_cfg_data - config data to setup cpu clocks @@ -28,38 +33,4 @@ struct exynos_cpuclk_cfg_data { unsigned long div1; }; -/** - * struct exynos_cpuclk - information about clock supplied to a CPU core - * @hw: handle between CCF and CPU clock - * @alt_parent: alternate parent clock to use when switching the speed - * of the primary parent clock - * @ctrl_base: base address of the clock controller - * @lock: cpu clock domain register access lock - * @cfg: cpu clock rate configuration data - * @num_cfgs: number of array elements in @cfg array - * @clk_nb: clock notifier registered for changes in clock speed of the - * primary parent clock - * @flags: configuration flags for the CPU clock - * - * This structure holds information required for programming the CPU clock for - * various clock speeds. - */ -struct exynos_cpuclk { - struct clk_hw hw; - const struct clk_hw *alt_parent; - void __iomem *ctrl_base; - spinlock_t *lock; - const struct exynos_cpuclk_cfg_data *cfg; - const unsigned long num_cfgs; - struct notifier_block clk_nb; - unsigned long flags; - -/* The CPU clock registers have DIV1 configuration register */ -#define CLK_CPU_HAS_DIV1 (1 << 0) -/* When ALT parent is active, debug clocks need safe divider values */ -#define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1) -/* The CPU clock registers have Exynos5433-compatible layout */ -#define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2) -}; - #endif /* __SAMSUNG_CLK_CPU_H */