From patchwork Tue Feb 27 14:55:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13573962 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCD171487D6; Tue, 27 Feb 2024 14:55:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709045744; cv=none; b=sTgHCgDWfvyA4e4H+TS+mOfawwUw7WJGKQ4SVrLJHEMlpNxBggSnE2RLvGT2Fs1b/sYHI5FybwTJWvypeb46egM5fOka5wMucAetvDT/CEJbSeQeTDT0PnxSrbbemAlnE+/m/goK9hxP6ElrAyCBxSOoe9/k2klNzLmOnw6AFyc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709045744; c=relaxed/simple; bh=na5iUFUdCcxo/XeKMDsWD2m8gyrN1SLEJxFdOBZFpes=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SnDZqUPda1asElFAd4oV/iI2HTKIe0N3ml8njD2w3/sXjoPj7NuSXleuKkETSF0bT0OsKrRUEIXs83Ff2m/C6Jmuq8ZG0KpQRwV18Acj+wEXYX5uOulirUaiS9ETKa4bOAQJLZEGD+Xyv/cjXHfk5iFAILUaocWg/LYSDnAduDs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=CA5TOEJG; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="CA5TOEJG" Received: by mail.gandi.net (Postfix) with ESMTPSA id 627FB20002; Tue, 27 Feb 2024 14:55:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1709045740; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YnALdwStqz9eKISqFy6qQHCMwj31QlMpXRX8xAVY3EI=; b=CA5TOEJGwdunwWTZTWjVnvvQlRANwYYWeXzmQU9H6pkot6bVEJXg8BWt7wwvq+Lz/wI0Bp qNVE45M4wOrZQC3AMgfonszmOCCBS3r4k414ucDRW8CKejiHULFfq3zEuNFI0eUpA9ZMp4 TV6bqv1bkdiKXr23oPaHrIW7RZmRA9RO1LNLOfMoFH0HHwY9WP8VrYFopTkZIkY9roE8F3 vizvdk3MawZ3YeqthUcJCF/TvKTuifuwego8XSUG9O3hLDw37G2HZqLBAjJe0RZmbYtAns U6ywAkbwpjstvzfnt6TN2639uScwAVUkIAO1FkDeKNaINbM83eGOonCJfwLj+A== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 27 Feb 2024 15:55:28 +0100 Subject: [PATCH v8 07/10] MIPS: mobileye: eyeq5: add OLB syscon node Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240227-mbly-clk-v8-7-c57fbda7664a@bootlin.com> References: <20240227-mbly-clk-v8-0-c57fbda7664a@bootlin.com> In-Reply-To: <20240227-mbly-clk-v8-0-c57fbda7664a@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com The OLB ("Other Logic Block") is a syscon region hosting the clock, reset and pin controllers. It contains registers such as I2C speed mode that need to be accessible by other nodes. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 6cc5980e2fa1..e82d2a57f6da 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -100,6 +100,14 @@ uart2: serial@a00000 { clock-names = "uartclk", "apb_pclk"; }; + olb: system-controller@e00000 { + compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd"; + reg = <0 0xe00000 0x0 0x400>; + ranges = <0x0 0x0 0xe00000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; + gic: interrupt-controller@140000 { compatible = "mti,gic"; reg = <0x0 0x140000 0x0 0x20000>;