| Message ID | 20240228-imx95-blk-ctl-v1-1-9b5ae3c14d83@nxp.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add support i.MX95 BLK CTL module clock features | expand |
On Wed, 28 Feb 2024 12:31:04 +0800, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > i.MX95 includes BLK CTL module in several MIXes, such as VPU_CSR in > VPUMIX, BLK_CTRL_NETCMIX in NETCMIX, CAMERA_CSR in CAMERAMIX and etc. > > The BLK CTL module is used for various settings of a specific MIX, such > as clock, QoS and etc. > > This patch is to add some BLK CTL modules that has clock features. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > .../devicetree/bindings/clock/imx95-blk-ctl.yaml | 61 ++++++++++++++++++++++ > include/dt-bindings/clock/nxp,imx95-clock.h | 32 ++++++++++++ > 2 files changed, 93 insertions(+) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/clock/imx95-blk-ctl.example.dtb: /example-0/syscon@4c410000: failed to match any schema with compatible: ['fsl,imx95-vpumix-blk-ctrl', 'syscon'] doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240228-imx95-blk-ctl-v1-1-9b5ae3c14d83@nxp.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
diff --git a/Documentation/devicetree/bindings/clock/imx95-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/imx95-blk-ctl.yaml new file mode 100644 index 000000000000..179bdd33504c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx95-blk-ctl.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx95-blk-ctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX95 Block Control + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +properties: + compatible: + items: + - enum: + - nxp,imx95-cameramix-csr + - nxp,imx95-display-master-csr + - nxp,imx95-dispmix-lvds-csr + - nxp,imx95-dispmix-csr + - nxp,imx95-netcmix-blk-ctrl + - nxp,imx95-vpumix-csr + - const: syscon + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See + include/dt-bindings/clock/nxp,imx95-clock.h + + mux-controller: + type: object + $ref: /schemas/mux/reg-mux.yaml + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + #include <dt-bindings/clock/nxp,imx95-clock.h> + + syscon@4c410000 { + compatible = "fsl,imx95-vpumix-blk-ctrl", "syscon"; + reg = <0x4c410000 0x10000>; + #clock-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h b/include/dt-bindings/clock/nxp,imx95-clock.h new file mode 100644 index 000000000000..09120e098a97 --- /dev/null +++ b/include/dt-bindings/clock/nxp,imx95-clock.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Copyright 2024 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX95_H +#define __DT_BINDINGS_CLOCK_IMX95_H + +#define IMX95_CLK_DISPMIX_ENG0_SEL 0 +#define IMX95_CLK_DISPMIX_ENG1_SEL 1 +#define IMX95_CLK_DISPMIX_END 2 + +#define IMX95_CLK_DISPMIX_LVDS_PHY_DIV 0 +#define IMX95_CLK_DISPMIX_LVDS_CH0_GATE 1 +#define IMX95_CLK_DISPMIX_LVDS_CH1_GATE 2 +#define IMX95_CLK_DISPMIX_PIX_DI0_GATE 3 +#define IMX95_CLK_DISPMIX_PIX_DI1_GATE 4 +#define IMX95_CLK_DISPMIX_LVDS_CSR_END 5 + +#define IMX95_CLK_VPUBLK_WAVE 0 +#define IMX95_CLK_VPUBLK_JPEG_ENC 1 +#define IMX95_CLK_VPUBLK_JPEG_DEC 2 +#define IMX95_CLK_VPUBLK_END 3 + +#define IMX95_CLK_CAMBLK_CSI2_FOR0 0 +#define IMX95_CLK_CAMBLK_CSI2_FOR1 1 +#define IMX95_CLK_CAMBLK_ISP_AXI 2 +#define IMX95_CLK_CAMBLK_ISP_PIXEL 3 +#define IMX95_CLK_CAMBLK_ISP 4 +#define IMX95_CLK_CAMBLK_END 5 + +#endif /* __DT_BINDINGS_CLOCK_IMX95_H */