| Message ID | 20240229-camcc-support-sm8150-v1-1-8c28c6c87990@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | clk: qcom: sm8150: Add camera clock controller support for SM8150 | expand |
On 29.02.2024 06:38, Satya Priya Kakitapalli wrote: > The PLL_POST_DIV_MASK should be 0 to (width - 1) bits. Fix it. > > Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider") > Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> > --- This makes sense if 'width' is what it says! The change also has an opportunity to fix a whole lot of bugs.. Please add `Cc: stable@vger.kernel.org`. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 8a412ef47e16..8dc3b8774b8e 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -40,7 +40,7 @@ #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) # define PLL_POST_DIV_SHIFT 8 -# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0) +# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) # define PLL_ALPHA_EN BIT(24) # define PLL_ALPHA_MODE BIT(25) # define PLL_VCO_SHIFT 20
The PLL_POST_DIV_MASK should be 0 to (width - 1) bits. Fix it. Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> --- drivers/clk/qcom/clk-alpha-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)