| Message ID | 20240413152013.22307-4-quic_jkona@quicinc.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | PM: domains: Add control for switching back and forth to HW control | expand |
On 13/04/2024 16:20, Jagadeesh Kona wrote: > Some GDSC client drivers require the GDSC mode to be switched dynamically > to HW mode at runtime to gain the power benefits. Typically such client > drivers require the GDSC to be brought up in SW mode initially to enable > the required dependent clocks and configure the hardware to proper state. > Once initial hardware set up is done, they switch the GDSC to HW mode to > save power. At the end of usecase, they switch the GDSC back to SW mode > and disable the GDSC. > > Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and > get_hwmode_dev callbacks for GDSC's whose respective client drivers > require the GDSC mode to be switched dynamically at runtime using > dev_pm_genpd_set_hwmode() API. > > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > drivers/clk/qcom/gdsc.c | 37 +++++++++++++++++++++++++++++++++++++ > drivers/clk/qcom/gdsc.h | 1 + > 2 files changed, 38 insertions(+) > > diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c > index df9618ab7eea..c5f6be8181d8 100644 > --- a/drivers/clk/qcom/gdsc.c > +++ b/drivers/clk/qcom/gdsc.c > @@ -363,6 +363,39 @@ static int gdsc_disable(struct generic_pm_domain *domain) > return 0; > } > > +static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct device *dev, bool mode) > +{ > + struct gdsc *sc = domain_to_gdsc(domain); > + int ret; > + > + ret = gdsc_hwctrl(sc, mode); > + if (ret) > + return ret; > + > + /* Wait for 1usec for mode transition to properly complete */ > + udelay(1); A delay I suspect you don't need - if the HW spec says "takes 1 usec for this to take effect" that's 1 usec from io write completion from APSS to another system agent. You poll for the state transition down below anyway. I'd be pretty certain that's a redundant delay. > + > + /* > + * When GDSC is switched to HW mode, HW can disable the GDSC. > + * When GDSC is switched back to SW mode, the GDSC will be enabled > + * again, hence need to poll for GDSC to complete the power up. > + */ > + if (!mode) > + return gdsc_poll_status(sc, GDSC_ON); > + > + return 0; > +} Other than that, seems fine. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
On 4/24/2024 5:18 AM, Bryan O'Donoghue wrote: > On 13/04/2024 16:20, Jagadeesh Kona wrote: >> Some GDSC client drivers require the GDSC mode to be switched dynamically >> to HW mode at runtime to gain the power benefits. Typically such client >> drivers require the GDSC to be brought up in SW mode initially to enable >> the required dependent clocks and configure the hardware to proper state. >> Once initial hardware set up is done, they switch the GDSC to HW mode to >> save power. At the end of usecase, they switch the GDSC back to SW mode >> and disable the GDSC. >> >> Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and >> get_hwmode_dev callbacks for GDSC's whose respective client drivers >> require the GDSC mode to be switched dynamically at runtime using >> dev_pm_genpd_set_hwmode() API. >> >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >> --- >> drivers/clk/qcom/gdsc.c | 37 +++++++++++++++++++++++++++++++++++++ >> drivers/clk/qcom/gdsc.h | 1 + >> 2 files changed, 38 insertions(+) >> >> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c >> index df9618ab7eea..c5f6be8181d8 100644 >> --- a/drivers/clk/qcom/gdsc.c >> +++ b/drivers/clk/qcom/gdsc.c >> @@ -363,6 +363,39 @@ static int gdsc_disable(struct generic_pm_domain >> *domain) >> return 0; >> } >> +static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct >> device *dev, bool mode) >> +{ >> + struct gdsc *sc = domain_to_gdsc(domain); >> + int ret; >> + >> + ret = gdsc_hwctrl(sc, mode); >> + if (ret) >> + return ret; >> + >> + /* Wait for 1usec for mode transition to properly complete */ >> + udelay(1); > > A delay I suspect you don't need - if the HW spec says "takes 1 usec for > this to take effect" that's 1 usec from io write completion from APSS to > another system agent. > > You poll for the state transition down below anyway. > > I'd be pretty certain that's a redundant delay. > Thanks Bryan for your review! This 1usec delay is needed every time GDSC is moved in and out of HW control mode and the reason for same is explained in one of the older gdsc driver change at below link https://lore.kernel.org/all/1484027679-18397-1-git-send-email-rnayak@codeaurora.org/ Thanks, Jagadeesh >> + >> + /* >> + * When GDSC is switched to HW mode, HW can disable the GDSC. >> + * When GDSC is switched back to SW mode, the GDSC will be enabled >> + * again, hence need to poll for GDSC to complete the power up. >> + */ >> + if (!mode) >> + return gdsc_poll_status(sc, GDSC_ON); >> + >> + return 0; >> +} > > Other than that, seems fine. > > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> >
On 24/04/2024 10:47, Jagadeesh Kona wrote: > > > On 4/24/2024 5:18 AM, Bryan O'Donoghue wrote: >> On 13/04/2024 16:20, Jagadeesh Kona wrote: >>> Some GDSC client drivers require the GDSC mode to be switched >>> dynamically >>> to HW mode at runtime to gain the power benefits. Typically such client >>> drivers require the GDSC to be brought up in SW mode initially to enable >>> the required dependent clocks and configure the hardware to proper >>> state. >>> Once initial hardware set up is done, they switch the GDSC to HW mode to >>> save power. At the end of usecase, they switch the GDSC back to SW mode >>> and disable the GDSC. >>> >>> Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and >>> get_hwmode_dev callbacks for GDSC's whose respective client drivers >>> require the GDSC mode to be switched dynamically at runtime using >>> dev_pm_genpd_set_hwmode() API. >>> >>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>> --- >>> drivers/clk/qcom/gdsc.c | 37 +++++++++++++++++++++++++++++++++++++ >>> drivers/clk/qcom/gdsc.h | 1 + >>> 2 files changed, 38 insertions(+) >>> >>> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c >>> index df9618ab7eea..c5f6be8181d8 100644 >>> --- a/drivers/clk/qcom/gdsc.c >>> +++ b/drivers/clk/qcom/gdsc.c >>> @@ -363,6 +363,39 @@ static int gdsc_disable(struct generic_pm_domain >>> *domain) >>> return 0; >>> } >>> +static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct >>> device *dev, bool mode) >>> +{ >>> + struct gdsc *sc = domain_to_gdsc(domain); >>> + int ret; >>> + >>> + ret = gdsc_hwctrl(sc, mode); >>> + if (ret) >>> + return ret; >>> + >>> + /* Wait for 1usec for mode transition to properly complete */ >>> + udelay(1); >> >> A delay I suspect you don't need - if the HW spec says "takes 1 usec >> for this to take effect" that's 1 usec from io write completion from >> APSS to another system agent. >> >> You poll for the state transition down below anyway. >> >> I'd be pretty certain that's a redundant delay. >> > > Thanks Bryan for your review! > > This 1usec delay is needed every time GDSC is moved in and out of HW > control mode and the reason for same is explained in one of the older > gdsc driver change at below link > > https://lore.kernel.org/all/1484027679-18397-1-git-send-email-rnayak@codeaurora.org/ > Right. If that is your precedent then you seem to be missing the mb(); between gdsc_hwctrl(); /* mb(); here */ and this udelay(1); --- bod
On 4/24/2024 3:25 PM, Bryan O'Donoghue wrote: > On 24/04/2024 10:47, Jagadeesh Kona wrote: >> >> >> On 4/24/2024 5:18 AM, Bryan O'Donoghue wrote: >>> On 13/04/2024 16:20, Jagadeesh Kona wrote: >>>> Some GDSC client drivers require the GDSC mode to be switched >>>> dynamically >>>> to HW mode at runtime to gain the power benefits. Typically such client >>>> drivers require the GDSC to be brought up in SW mode initially to >>>> enable >>>> the required dependent clocks and configure the hardware to proper >>>> state. >>>> Once initial hardware set up is done, they switch the GDSC to HW >>>> mode to >>>> save power. At the end of usecase, they switch the GDSC back to SW mode >>>> and disable the GDSC. >>>> >>>> Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and >>>> get_hwmode_dev callbacks for GDSC's whose respective client drivers >>>> require the GDSC mode to be switched dynamically at runtime using >>>> dev_pm_genpd_set_hwmode() API. >>>> >>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>>> --- >>>> drivers/clk/qcom/gdsc.c | 37 +++++++++++++++++++++++++++++++++++++ >>>> drivers/clk/qcom/gdsc.h | 1 + >>>> 2 files changed, 38 insertions(+) >>>> >>>> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c >>>> index df9618ab7eea..c5f6be8181d8 100644 >>>> --- a/drivers/clk/qcom/gdsc.c >>>> +++ b/drivers/clk/qcom/gdsc.c >>>> @@ -363,6 +363,39 @@ static int gdsc_disable(struct >>>> generic_pm_domain *domain) >>>> return 0; >>>> } >>>> +static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct >>>> device *dev, bool mode) >>>> +{ >>>> + struct gdsc *sc = domain_to_gdsc(domain); >>>> + int ret; >>>> + >>>> + ret = gdsc_hwctrl(sc, mode); >>>> + if (ret) >>>> + return ret; >>>> + >>>> + /* Wait for 1usec for mode transition to properly complete */ >>>> + udelay(1); >>> >>> A delay I suspect you don't need - if the HW spec says "takes 1 usec >>> for this to take effect" that's 1 usec from io write completion from >>> APSS to another system agent. >>> >>> You poll for the state transition down below anyway. >>> >>> I'd be pretty certain that's a redundant delay. >>> >> >> Thanks Bryan for your review! >> >> This 1usec delay is needed every time GDSC is moved in and out of HW >> control mode and the reason for same is explained in one of the older >> gdsc driver change at below link >> >> https://lore.kernel.org/all/1484027679-18397-1-git-send-email-rnayak@codeaurora.org/ >> > > Right. > > If that is your precedent then you seem to be missing the mb(); between > > gdsc_hwctrl(); > > /* mb(); here */ > > and this > > udelay(1); > Sorry, earlier I shared the link to base patch series which has mb() used, but in the mainlined series of the same patch mb() is removed as per the review comments. Please find the mainlined series link:- https://lore.kernel.org/all/1485145581-517-1-git-send-email-rnayak@codeaurora.org/ Thanks, Jagadeesh > --- > bod
On 4/24/24 12:27, Jagadeesh Kona wrote: > > > On 4/24/2024 3:25 PM, Bryan O'Donoghue wrote: >> On 24/04/2024 10:47, Jagadeesh Kona wrote: >>> >>> >>> On 4/24/2024 5:18 AM, Bryan O'Donoghue wrote: >>>> On 13/04/2024 16:20, Jagadeesh Kona wrote: >>>>> Some GDSC client drivers require the GDSC mode to be switched dynamically >>>>> to HW mode at runtime to gain the power benefits. Typically such client >>>>> drivers require the GDSC to be brought up in SW mode initially to enable >>>>> the required dependent clocks and configure the hardware to proper state. >>>>> Once initial hardware set up is done, they switch the GDSC to HW mode to >>>>> save power. At the end of usecase, they switch the GDSC back to SW mode >>>>> and disable the GDSC. >>>>> >>>>> Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and >>>>> get_hwmode_dev callbacks for GDSC's whose respective client drivers >>>>> require the GDSC mode to be switched dynamically at runtime using >>>>> dev_pm_genpd_set_hwmode() API. >>>>> >>>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>>>> --- >>>>> drivers/clk/qcom/gdsc.c | 37 +++++++++++++++++++++++++++++++++++++ >>>>> drivers/clk/qcom/gdsc.h | 1 + >>>>> 2 files changed, 38 insertions(+) >>>>> >>>>> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c >>>>> index df9618ab7eea..c5f6be8181d8 100644 >>>>> --- a/drivers/clk/qcom/gdsc.c >>>>> +++ b/drivers/clk/qcom/gdsc.c >>>>> @@ -363,6 +363,39 @@ static int gdsc_disable(struct generic_pm_domain *domain) >>>>> return 0; >>>>> } >>>>> +static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct device *dev, bool mode) >>>>> +{ >>>>> + struct gdsc *sc = domain_to_gdsc(domain); >>>>> + int ret; >>>>> + >>>>> + ret = gdsc_hwctrl(sc, mode); >>>>> + if (ret) >>>>> + return ret; >>>>> + >>>>> + /* Wait for 1usec for mode transition to properly complete */ >>>>> + udelay(1); >>>> >>>> A delay I suspect you don't need - if the HW spec says "takes 1 usec for this to take effect" that's 1 usec from io write completion from APSS to another system agent. >>>> >>>> You poll for the state transition down below anyway. >>>> >>>> I'd be pretty certain that's a redundant delay. >>>> >>> >>> Thanks Bryan for your review! >>> >>> This 1usec delay is needed every time GDSC is moved in and out of HW control mode and the reason for same is explained in one of the older gdsc driver change at below link >>> >>> https://lore.kernel.org/all/1484027679-18397-1-git-send-email-rnayak@codeaurora.org/ >>> >> >> Right. >> >> If that is your precedent then you seem to be missing the mb(); between >> >> gdsc_hwctrl(); >> >> /* mb(); here */ >> >> and this >> >> udelay(1); >> > > Sorry, earlier I shared the link to base patch series which has mb() used, but in the mainlined series of the same patch mb() is removed as per the review comments. > > Please find the mainlined series link:- > https://lore.kernel.org/all/1485145581-517-1-git-send-email-rnayak@codeaurora.org/ Mostly because mb is a solution to a different problem. See this talk for more details: https://youtu.be/i6DayghhA8Q Konrad
On 4/24/24 14:22, Konrad Dybcio wrote: > > > On 4/24/24 12:27, Jagadeesh Kona wrote: >> >> >> On 4/24/2024 3:25 PM, Bryan O'Donoghue wrote: >>> On 24/04/2024 10:47, Jagadeesh Kona wrote: >>>> >>>> >>>> On 4/24/2024 5:18 AM, Bryan O'Donoghue wrote: >>>>> On 13/04/2024 16:20, Jagadeesh Kona wrote: >>>>>> Some GDSC client drivers require the GDSC mode to be switched dynamically >>>>>> to HW mode at runtime to gain the power benefits. Typically such client >>>>>> drivers require the GDSC to be brought up in SW mode initially to enable >>>>>> the required dependent clocks and configure the hardware to proper state. >>>>>> Once initial hardware set up is done, they switch the GDSC to HW mode to >>>>>> save power. At the end of usecase, they switch the GDSC back to SW mode >>>>>> and disable the GDSC. >>>>>> >>>>>> Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and >>>>>> get_hwmode_dev callbacks for GDSC's whose respective client drivers >>>>>> require the GDSC mode to be switched dynamically at runtime using >>>>>> dev_pm_genpd_set_hwmode() API. >>>>>> >>>>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>>>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>>>>> --- >>>>>> drivers/clk/qcom/gdsc.c | 37 +++++++++++++++++++++++++++++++++++++ >>>>>> drivers/clk/qcom/gdsc.h | 1 + >>>>>> 2 files changed, 38 insertions(+) >>>>>> >>>>>> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c >>>>>> index df9618ab7eea..c5f6be8181d8 100644 >>>>>> --- a/drivers/clk/qcom/gdsc.c >>>>>> +++ b/drivers/clk/qcom/gdsc.c >>>>>> @@ -363,6 +363,39 @@ static int gdsc_disable(struct generic_pm_domain *domain) >>>>>> return 0; >>>>>> } >>>>>> +static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct device *dev, bool mode) >>>>>> +{ >>>>>> + struct gdsc *sc = domain_to_gdsc(domain); >>>>>> + int ret; >>>>>> + >>>>>> + ret = gdsc_hwctrl(sc, mode); >>>>>> + if (ret) >>>>>> + return ret; >>>>>> + >>>>>> + /* Wait for 1usec for mode transition to properly complete */ >>>>>> + udelay(1); >>>>> >>>>> A delay I suspect you don't need - if the HW spec says "takes 1 usec for this to take effect" that's 1 usec from io write completion from APSS to another system agent. >>>>> >>>>> You poll for the state transition down below anyway. >>>>> >>>>> I'd be pretty certain that's a redundant delay. >>>>> >>>> >>>> Thanks Bryan for your review! >>>> >>>> This 1usec delay is needed every time GDSC is moved in and out of HW control mode and the reason for same is explained in one of the older gdsc driver change at below link >>>> >>>> https://lore.kernel.org/all/1484027679-18397-1-git-send-email-rnayak@codeaurora.org/ >>>> >>> >>> Right. >>> >>> If that is your precedent then you seem to be missing the mb(); between >>> >>> gdsc_hwctrl(); >>> >>> /* mb(); here */ >>> >>> and this >>> >>> udelay(1); >>> >> >> Sorry, earlier I shared the link to base patch series which has mb() used, but in the mainlined series of the same patch mb() is removed as per the review comments. >> >> Please find the mainlined series link:- >> https://lore.kernel.org/all/1485145581-517-1-git-send-email-rnayak@codeaurora.org/ > > Mostly because mb is a solution to a different problem. See this talk > for more details: > > https://youtu.be/i6DayghhA8Q (long story short: you want to read back the register right after writing to make sure things arrive at the hardware when you expect it to) Konrad
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index df9618ab7eea..c5f6be8181d8 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -363,6 +363,39 @@ static int gdsc_disable(struct generic_pm_domain *domain) return 0; } +static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct device *dev, bool mode) +{ + struct gdsc *sc = domain_to_gdsc(domain); + int ret; + + ret = gdsc_hwctrl(sc, mode); + if (ret) + return ret; + + /* Wait for 1usec for mode transition to properly complete */ + udelay(1); + + /* + * When GDSC is switched to HW mode, HW can disable the GDSC. + * When GDSC is switched back to SW mode, the GDSC will be enabled + * again, hence need to poll for GDSC to complete the power up. + */ + if (!mode) + return gdsc_poll_status(sc, GDSC_ON); + + return 0; +} + +static bool gdsc_get_hwmode(struct generic_pm_domain *domain, struct device *dev) +{ + struct gdsc *sc = domain_to_gdsc(domain); + u32 val; + + regmap_read(sc->regmap, sc->gdscr, &val); + + return !!(val & HW_CONTROL_MASK); +} + static int gdsc_init(struct gdsc *sc) { u32 mask, val; @@ -451,6 +484,10 @@ static int gdsc_init(struct gdsc *sc) sc->pd.power_off = gdsc_disable; if (!sc->pd.power_on) sc->pd.power_on = gdsc_enable; + if (sc->flags & HW_CTRL_TRIGGER) { + sc->pd.set_hwmode_dev = gdsc_set_hwmode; + sc->pd.get_hwmode_dev = gdsc_get_hwmode; + } ret = pm_genpd_init(&sc->pd, NULL, !on); if (ret) diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 803512688336..1e2779b823d1 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -67,6 +67,7 @@ struct gdsc { #define ALWAYS_ON BIT(6) #define RETAIN_FF_ENABLE BIT(7) #define NO_RET_PERIPH BIT(8) +#define HW_CTRL_TRIGGER BIT(9) struct reset_controller_dev *rcdev; unsigned int *resets; unsigned int reset_count;