clk: sophgo: avoid open-coded 64-bit division

Commit Message

Arnd Bergmann April 15, 2024, 1:45 p.m. UTC

From: Arnd Bergmann <[e-mail]>

On 32-bit architectures, the 64-bit division leads to a link failure:

arm-linux-gnueabi-ld: drivers/clk/sophgo/clk-cv18xx-pll.o: in function `fpll_calc_rate':
clk-cv18xx-pll.c:(.text.fpll_calc_rate+0x26): undefined reference to `__aeabi_uldivmod'

This one is not called in a fast path, and there is already another div_u64()
variant used in the same function, so convert it to div64_u64_rem().

Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
Signed-off-by: Arnd Bergmann <[e-mail]>
---
 drivers/clk/sophgo/clk-cv18xx-pll.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

Comments

Inochi Amaoto April 15, 2024, 10:30 p.m. UTC | #1

On Mon, Apr 15, 2024 at 03:45:20PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <[e-mail]>
> 
> On 32-bit architectures, the 64-bit division leads to a link failure:
> 
> arm-linux-gnueabi-ld: drivers/clk/sophgo/clk-cv18xx-pll.o: in function `fpll_calc_rate':
> clk-cv18xx-pll.c:(.text.fpll_calc_rate+0x26): undefined reference to `__aeabi_uldivmod'
> 
> This one is not called in a fast path, and there is already another div_u64()
> variant used in the same function, so convert it to div64_u64_rem().
> 
> Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
> Signed-off-by: Arnd Bergmann <[e-mail]>

There is already a fix patch:
https://lore.kernel.org/all/[e-mail]/

Inochi Amaoto April 17, 2024, 11:12 a.m. UTC | #2

On Tue, Apr 16, 2024 at 06:30:42AM GMT, Inochi Amaoto wrote:
> On Mon, Apr 15, 2024 at 03:45:20PM +0200, Arnd Bergmann wrote:
> > From: Arnd Bergmann <[e-mail]>
> > 
> > On 32-bit architectures, the 64-bit division leads to a link failure:
> > 
> > arm-linux-gnueabi-ld: drivers/clk/sophgo/clk-cv18xx-pll.o: in function `fpll_calc_rate':
> > clk-cv18xx-pll.c:(.text.fpll_calc_rate+0x26): undefined reference to `__aeabi_uldivmod'
> > 
> > This one is not called in a fast path, and there is already another div_u64()
> > variant used in the same function, so convert it to div64_u64_rem().
> > 
> > Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
> > Signed-off-by: Arnd Bergmann <[e-mail]>
> 
> There is already a fix patch:
> https://lore.kernel.org/all/[e-mail]/

Hi Arnd,

I have looked your patch again and think your patch is better
than mine. So I decided to drop my patch and favor yours.

LGTM. And there are some necessary tags.

Reviewed-by: Inochi Amaoto <[e-mail]>
Reported-by: kernel test robot <[e-mail]>
Closes: https://lore.kernel.org/oe-kbuild-all/[e-mail]/
Closes: https://lore.kernel.org/oe-kbuild-all/[e-mail]/

Stephen Boyd April 19, 2024, 9:38 p.m. UTC | #3

Quoting Arnd Bergmann (2024-04-15 06:45:20)
> From: Arnd Bergmann <[e-mail]>
> 
> On 32-bit architectures, the 64-bit division leads to a link failure:
> 
> arm-linux-gnueabi-ld: drivers/clk/sophgo/clk-cv18xx-pll.o: in function `fpll_calc_rate':
> clk-cv18xx-pll.c:(.text.fpll_calc_rate+0x26): undefined reference to `__aeabi_uldivmod'
> 
> This one is not called in a fast path, and there is already another div_u64()
> variant used in the same function, so convert it to div64_u64_rem().
> 
> Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
> Signed-off-by: Arnd Bergmann <[e-mail]>
> ---

Applied to clk-next

Patch

diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c
index c546dad1791c..29e24098bf5f 100644
--- a/drivers/clk/sophgo/clk-cv18xx-pll.c
+++ b/drivers/clk/sophgo/clk-cv18xx-pll.c
@@ -205,8 +205,7 @@  static unsigned long fpll_calc_rate(unsigned long parent_rate,
 	unsigned long rate;
 
 	dividend <<= PLL_SYN_FACTOR_DOT_POS - 1;
-	rate = dividend / factor;
-	dividend %= factor;
+	rate = div64_u64_rem(dividend, factor, &dividend);
 
 	if (is_full_parent) {
 		dividend <<= 1;