From patchwork Wed Apr 24 18:42:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= X-Patchwork-Id: 13642369 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 393E31BF40; Wed, 24 Apr 2024 18:42:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713984157; cv=none; b=ntyqxLCSZJ3TcSsPXxDoo08Efld7uv6h3CudbGSh0bfZ39O0l3J9vv3P9H3uCsOzNdjGSQKCYcQdfV2gzbGA/pHfCjA7ih1qLWYyXkBC5w2i7ao5tHUWIKcjT8OPLbwifvlUtBiKDYAtUs8atQcz1f2TKNEpeSLO/I9REVw3xe4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713984157; c=relaxed/simple; bh=jmHgAIQB5ZqaxVOO+9q+xc3becTS+uCbIZTTYikcH5I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AOokZA3XxXbgWZe2OxK072uc8kzhcF5fj3UtkJ65+rFqcvZXO0+9g56J4ZmWRbO449YMDPksiB7M1AfCdUwhkb1eDPVAkJXkOlkHghhNgf5CSHI9rT7iaNk1zPoc/5D1sqgq0pVvyAx0+Mjjq5ZjkAlDRAmS9XBSq0xs2KYxq4w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NdkiAoUo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NdkiAoUo" Received: by smtp.kernel.org (Postfix) with ESMTPS id B65DCC4AF15; Wed, 24 Apr 2024 18:42:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713984156; bh=jmHgAIQB5ZqaxVOO+9q+xc3becTS+uCbIZTTYikcH5I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NdkiAoUoiGW/HtgaPNSFTpC89L+gi4UnROPc9ONn/l50ROu/2dnUC/TDfkWamgzwv TJH705CG9v/t3/yBzOZuqSrCb5N/dlU064iIfgKJ/EnUk9b3PuJlP8GTF3WcVCvJVq KUMJUBc9r9i/J67A9FzzEg8KPVQx1/6Oyur6UCiF9LGmwd18SKuJQlqpUlT4bIbeTS zBNgXFYT/DEuvsnj+kt8ttFabwNbED5IwiIFfKZATb4IO2lW+bEAqyMrvzs1P8gGBG 29PbkuDIPwIhnTy6enaRKS756rFC4J3bcVr65XvndlkhZyXTLr3XMJ6US2vDQzjCuO 9mI9sICgH6MYg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A387FC25B10; Wed, 24 Apr 2024 18:42:36 +0000 (UTC) From: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= Date: Wed, 24 Apr 2024 20:42:31 +0200 Subject: [PATCH v10 04/12] dt-bindings: clock: Add Marvell PXA1908 clock bindings Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240424-pxa1908-lkml-v10-4-36cdfb5841f9@skole.hr> References: <20240424-pxa1908-lkml-v10-0-36cdfb5841f9@skole.hr> In-Reply-To: <20240424-pxa1908-lkml-v10-0-36cdfb5841f9@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tony Lindgren , Haojian Zhuang , =?utf-8?q?Duje_Mihanovi=C4=87?= , Lubomir Rintel , Catalin Marinas , Will Deacon , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , David Wronek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4973; i=duje.mihanovic@skole.hr; h=from:subject:message-id; bh=66ntIjJKW695WJvUGo70eRpNUwfBD1UMjW0Gy/wWSJQ=; b=owEBbQKS/ZANAwAIAZoRnrBCLZbhAcsmYgBmKVKU+rs4awadEa/CMjTSCZImdwH07bcW/pPGJ FFASl3TDd6JAjMEAAEIAB0WIQRT351NnD/hEPs2LXiaEZ6wQi2W4QUCZilSlAAKCRCaEZ6wQi2W 4eDaD/9hR4c1bPZtrP6ViCrChaIdPOdlTJzU3/t5bc63lFUZI8Y/FPaW/RL7PzRdEsYqzPrE5AB jO4l2F6rgHWWkISBDEHLRi45CFtbv9i/gPQQvP2CiL2Y03qZMIq0XFugKvpQ2EcUpBxYpzY9Zhp kvHibaBflY68aBXF2qosE67BQ0xdKwiVyRN4s/r7+U/LGwyU529/eWR/COtpRnJorp7pB85DwX9 lIS3QqKZPlhU/cj028FBddBuJ+K7PouZSaZlHmeChPM/Ld+gfSE4c+HAdZjVA16UgPiKTSoeVvi KtfrySTaYbFa98B3j3wqDjUP6f1rlVrQ8+DfkGTY97Ptqw8MRXCP7d8Vhxhbl34ihXZrnUluskv 64zWInUJHEjCWLYnICXM2DyEgHUWxaXV3AOG94VdfQ5Oh4AVQnTCXuSYj2Nyw+mAEhjPTQ9VhBx 3VoJ02jOHf+ddHdiukSvpJUZHwG/5vR+E2gAh2aFvMCfuCyT77Sl+bXiYZ3gwq/aZCwBF0gYb4N Sg+7AASTRK6x1y4soNmV4XymgCXrITVT80FVsStTcCNHfTnwLtt0eNdtzmtebRbuV8OvvRc/y87 lDyKzULF+6If/x6JFHDOtFwtHE+MuGCqBqXI/o5DoKcwL6qPjHHvfkv82HvXpXxOztqSV0qN923 de75CTcMPa/mMjg== X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=53DF9D4D9C3FE110FB362D789A119EB0422D96E1 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/default with auth_id=112 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanović Add dt bindings and documentation for the Marvell PXA1908 clock controller. Reviewed-by: Conor Dooley Reviewed-by: Stephen Boyd Signed-off-by: Duje Mihanović --- .../devicetree/bindings/clock/marvell,pxa1908.yaml | 48 ++++++++++++ include/dt-bindings/clock/marvell,pxa1908.h | 88 ++++++++++++++++++++++ 2 files changed, 136 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml new file mode 100644 index 000000000000..4e78933232b6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA1908 Clock Controllers + +maintainers: + - Duje Mihanović + +description: | + The PXA1908 clock subsystem generates and supplies clock to various + controllers within the PXA1908 SoC. The PXA1908 contains numerous clock + controller blocks, with the ones currently supported being APBC, APBCP, MPMU + and APMU roughly corresponding to internal buses. + + All these clock identifiers could be found in . + +properties: + compatible: + enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + - marvell,pxa1908-mpmu + - marvell,pxa1908-apmu + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # APMU block: + - | + clock-controller@d4282800 { + compatible = "marvell,pxa1908-apmu"; + reg = <0xd4282800 0x400>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindings/clock/marvell,pxa1908.h new file mode 100644 index 000000000000..fb15b0d0cd4c --- /dev/null +++ b/include/dt-bindings/clock/marvell,pxa1908.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +#ifndef __DTS_MARVELL_PXA1908_CLOCK_H +#define __DTS_MARVELL_PXA1908_CLOCK_H + +/* plls */ +#define PXA1908_CLK_CLK32 1 +#define PXA1908_CLK_VCTCXO 2 +#define PXA1908_CLK_PLL1_624 3 +#define PXA1908_CLK_PLL1_416 4 +#define PXA1908_CLK_PLL1_499 5 +#define PXA1908_CLK_PLL1_832 6 +#define PXA1908_CLK_PLL1_1248 7 +#define PXA1908_CLK_PLL1_D2 8 +#define PXA1908_CLK_PLL1_D4 9 +#define PXA1908_CLK_PLL1_D8 10 +#define PXA1908_CLK_PLL1_D16 11 +#define PXA1908_CLK_PLL1_D6 12 +#define PXA1908_CLK_PLL1_D12 13 +#define PXA1908_CLK_PLL1_D24 14 +#define PXA1908_CLK_PLL1_D48 15 +#define PXA1908_CLK_PLL1_D96 16 +#define PXA1908_CLK_PLL1_D13 17 +#define PXA1908_CLK_PLL1_32 18 +#define PXA1908_CLK_PLL1_208 19 +#define PXA1908_CLK_PLL1_117 20 +#define PXA1908_CLK_PLL1_416_GATE 21 +#define PXA1908_CLK_PLL1_624_GATE 22 +#define PXA1908_CLK_PLL1_832_GATE 23 +#define PXA1908_CLK_PLL1_1248_GATE 24 +#define PXA1908_CLK_PLL1_D2_GATE 25 +#define PXA1908_CLK_PLL1_499_EN 26 +#define PXA1908_CLK_PLL2VCO 27 +#define PXA1908_CLK_PLL2 28 +#define PXA1908_CLK_PLL2P 29 +#define PXA1908_CLK_PLL2VCODIV3 30 +#define PXA1908_CLK_PLL3VCO 31 +#define PXA1908_CLK_PLL3 32 +#define PXA1908_CLK_PLL3P 33 +#define PXA1908_CLK_PLL3VCODIV3 34 +#define PXA1908_CLK_PLL4VCO 35 +#define PXA1908_CLK_PLL4 36 +#define PXA1908_CLK_PLL4P 37 +#define PXA1908_CLK_PLL4VCODIV3 38 + +/* apb (apbc) peripherals */ +#define PXA1908_CLK_UART0 1 +#define PXA1908_CLK_UART1 2 +#define PXA1908_CLK_GPIO 3 +#define PXA1908_CLK_PWM0 4 +#define PXA1908_CLK_PWM1 5 +#define PXA1908_CLK_PWM2 6 +#define PXA1908_CLK_PWM3 7 +#define PXA1908_CLK_SSP0 8 +#define PXA1908_CLK_SSP1 9 +#define PXA1908_CLK_IPC_RST 10 +#define PXA1908_CLK_RTC 11 +#define PXA1908_CLK_TWSI0 12 +#define PXA1908_CLK_KPC 13 +#define PXA1908_CLK_SWJTAG 14 +#define PXA1908_CLK_SSP2 15 +#define PXA1908_CLK_TWSI1 16 +#define PXA1908_CLK_THERMAL 17 +#define PXA1908_CLK_TWSI3 18 + +/* apb (apbcp) peripherals */ +#define PXA1908_CLK_UART2 1 +#define PXA1908_CLK_TWSI2 2 +#define PXA1908_CLK_AICER 3 + +/* axi (apmu) peripherals */ +#define PXA1908_CLK_CCIC1 1 +#define PXA1908_CLK_ISP 2 +#define PXA1908_CLK_DSI1 3 +#define PXA1908_CLK_DISP1 4 +#define PXA1908_CLK_CCIC0 5 +#define PXA1908_CLK_SDH0 6 +#define PXA1908_CLK_SDH1 7 +#define PXA1908_CLK_USB 8 +#define PXA1908_CLK_NF 9 +#define PXA1908_CLK_CORE_DEBUG 10 +#define PXA1908_CLK_VPU 11 +#define PXA1908_CLK_GC 12 +#define PXA1908_CLK_SDH2 13 +#define PXA1908_CLK_GC2D 14 +#define PXA1908_CLK_TRACE 15 +#define PXA1908_CLK_DVC_DFC_DEBUG 16 + +#endif