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AJvYcCXvTvUvXd9KScQSrfMWbin9kLvzAgxoo2osYCG03sHy+ZNk7i3mfS5SY1XNSjkw1ueMfaz9Vi4yUq1BA2EZD4pnt5RGoJlYGSEWi5BUt9Tn7kXeNwc7T6XS7efIOPg2pcjPEZ73zfRKJBfy6TlRauaCkKAMbwZDtuHCWUViF3YDplTD2w== X-Gm-Message-State: AOJu0YwR5q6slP+0vud+yix68ODIszwvUmaBjjwoyTlXfqmW+hkygsXH pIoToitpKtbttNrBbpHsMasGB4WLWU9cIdvohp+KMqjQ7pXDB2U= X-Google-Smtp-Source: AGHT+IFljPNeI2NnGG45C+k3hGACkIN7MrrcjptnJgVqnmjgLGPcaqegGP1B5NCUyh20R+F22xanOQ== X-Received: by 2002:a05:6000:120d:b0:34d:8fac:9540 with SMTP id ffacd0b85a97d-34fca80df25mr5625135f8f.59.1715263621985; Thu, 09 May 2024 07:07:01 -0700 (PDT) Received: from U4.lan ([2a02:810b:f40:4600:b44:d8c3:6fa8:c46f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502baad058sm1793311f8f.66.2024.05.09.07.07.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 07:07:01 -0700 (PDT) From: Alex Bee To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alex Bee Subject: [PATCH v3 4/7] clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocks Date: Thu, 9 May 2024 16:06:50 +0200 Message-ID: <20240509140653.168591-5-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240509140653.168591-1-knaerzche@gmail.com> References: <20240509140653.168591-1-knaerzche@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The DSI controller needs this clock to be enabled in order to be able to access the registers. Make it critical for that purpose. Signed-off-by: Alex Bee --- changes since v1: - dropped patch changes since v2: -re-added patch drivers/clk/rockchip/clk-rk3128.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c index a20d1fd25e2a..d076b7971f33 100644 --- a/drivers/clk/rockchip/clk-rk3128.c +++ b/drivers/clk/rockchip/clk-rk3128.c @@ -563,6 +563,7 @@ static const char *const rk3128_critical_clocks[] __initconst = { "pclk_cpu", "aclk_peri", "hclk_peri", + "hclk_vio_h2p", "pclk_peri", "pclk_pmu", "sclk_timer5",