@@ -60,18 +60,6 @@ properties:
- const: dptx2_phy_pll_link_clk
- const: dptx2_phy_pll_vco_div_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
@@ -84,14 +72,12 @@ properties:
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
allOf:
+ - $ref: qcom,gcc.yaml#
- if:
not:
properties:
@@ -105,7 +91,7 @@ allOf:
clock-names:
maxItems: 7
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
Just like most of clock controllers, the SM8150 and others display clock controllers are also some variant of standard Qualcomm GCC, so reference common qcom,gcc.yaml schema to simplify the binding and unify it with others. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-)