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Wed, 19 Jun 2024 02:58:23 +0800 Received: from taln60.nuvoton.co.il (taln60 [10.191.1.180]) by taln58.nuvoton.co.il (Postfix) with ESMTP id 87C465F633; Tue, 18 Jun 2024 21:58:22 +0300 (IDT) Received: by taln60.nuvoton.co.il (Postfix, from userid 10070) id 833FBDC0726; Tue, 18 Jun 2024 21:58:22 +0300 (IDT) From: Tomer Maimon To: , , , , , , , , , CC: , , , , Tomer Maimon Subject: [PATCH v25 1/3] dt-bindings: reset: npcm: add clock properties Date: Tue, 18 Jun 2024 21:58:17 +0300 Message-ID: <20240618185819.2155595-2-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618185819.2155595-1-tmaimon77@gmail.com> References: <20240618185819.2155595-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NotSetDelaration: True X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: HK2PEPF00006FAF:EE_|KL1PR03MB8822:EE_ X-MS-Office365-Filtering-Correlation-Id: 7bd16319-27f4-4123-a73b-08dc8fc8a162 X-MS-Exchange-SenderADCheck: 2 X-MS-Exchange-AntiSpam-Relay: 1 X-Microsoft-Antispam: BCL:0;ARA:13230037|35950700013|48200799015|7416011|376011|7093399009|82310400023|61400799024|921017|35450700002; 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X-OriginatorOrg: nuvoton.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2024 18:58:24.3127 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7bd16319-27f4-4123-a73b-08dc8fc8a162 X-MS-Exchange-CrossTenant-Id: a3f24931-d403-4b4a-94f1-7d83ac638e07 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=a3f24931-d403-4b4a-94f1-7d83ac638e07;Ip=[211.75.126.7];Helo=[NTHCCAS01.nuvoton.com] X-MS-Exchange-CrossTenant-AuthSource: HK2PEPF00006FAF.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KL1PR03MB8822 This commit adds a 25MHz reference clock and clock-cell properties to the NPCM reset document. The addition is necessitated by the integration of the NPCM8xx clock auxiliary bus device into the NPCM reset driver. The inclusion of the NPCM8xx clock properties in the reset document is crucial as the reset block also serves as a clock provider for the NPCM8xx clock. This enhancement is intended to facilitate the use of the NPCM8xx clock driver. Signed-off-by: Tomer Maimon Reviewed-by: Rob Herring --- .../bindings/reset/nuvoton,npcm750-reset.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml index d82e65e37cc0..72523f1bbc18 100644 --- a/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml @@ -21,6 +21,13 @@ properties: '#reset-cells': const: 2 + '#clock-cells': + const: 1 + + clocks: + items: + - description: specify external 25MHz reference clock. + nuvoton,sysgcr: $ref: /schemas/types.yaml#/definitions/phandle description: a phandle to access GCR registers. @@ -39,6 +46,17 @@ required: - '#reset-cells' - nuvoton,sysgcr +if: + properties: + compatible: + contains: + enum: + - nuvoton,npcm845-reset +then: + required: + - '#clock-cells' + - clocks + additionalProperties: false examples: