Message ID | 20240625070536.3043630-8-quic_devipriy@quicinc.com (mailing list archive) |
---|---|
State | Not Applicable, archived |
Headers | show
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Tue, 25 Jun 2024 07:05:43 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTP id 45P75dWC013374; Tue, 25 Jun 2024 07:05:39 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3ywqpky2v2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jun 2024 07:05:39 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 45P75d26013354; Tue, 25 Jun 2024 07:05:39 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-devipriy-blr.qualcomm.com [10.131.37.37]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 45P75dEJ013349 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jun 2024 07:05:39 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 4059087) id ED889419C8; Tue, 25 Jun 2024 12:35:36 +0530 (+0530) From: Devi Priya <quic_devipriy@quicinc.com> To: andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konrad.dybcio@linaro.org, catalin.marinas@arm.com, will@kernel.org, p.zabel@pengutronix.de, richardcochran@gmail.com, geert+renesas@glider.be, dmitry.baryshkov@linaro.org, neil.armstrong@linaro.org, arnd@arndb.de, m.szyprowski@samsung.com, nfraprado@collabora.com, u-kumar1@ti.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org Cc: quic_devipriy@quicinc.com Subject: [PATCH V4 7/7] arm64: defconfig: Build NSS Clock Controller driver for IPQ9574 Date: Tue, 25 Jun 2024 12:35:36 +0530 Message-Id: <20240625070536.3043630-8-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625070536.3043630-1-quic_devipriy@quicinc.com> References: <20240625070536.3043630-1-quic_devipriy@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: <linux-clk.vger.kernel.org> List-Subscribe: <mailto:linux-clk+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-clk+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: T5-Y5Sd92CXB5SFillaX-3w6G1uKo4Ee X-Proofpoint-GUID: T5-Y5Sd92CXB5SFillaX-3w6G1uKo4Ee X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-25_03,2024-06-24_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 mlxscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=999 spamscore=0 clxscore=1011 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406250051 |
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Add NSS clock controller support for IPQ9574
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diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index dfaec2d4052c..40a5ea212518 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1300,6 +1300,7 @@ CONFIG_IPQ_GCC_5332=y CONFIG_IPQ_GCC_6018=y CONFIG_IPQ_GCC_8074=y CONFIG_IPQ_GCC_9574=y +CONFIG_IPQ_NSSCC_9574=m CONFIG_MSM_GCC_8916=y CONFIG_MSM_MMCC_8994=m CONFIG_MSM_GCC_8994=y
NSSCC driver is needed to enable the ethernet interfaces and not necessary for the bootup of the SoC, hence build it as a module. Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> --- Changes in V4: - No change arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+)