| Message ID | 20240702-camcc-support-sm8150-v2-2-4baf54ec7333@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | clk: qcom: sm8150: Add camera clock controller support for SM8150 | expand |
On Tue, Jul 02, 2024 at 09:20:40PM GMT, Satya Priya Kakitapalli wrote: > The Zonda PLL has a 16 bit signed alpha and in the cases where the alpha > value is greater than 0.5, the L value needs to be adjusted accordingly. > Thus update the logic for the same. > > Also, fix zonda set_rate failure when PLL is disabled. Currently, > clk_zonda_pll_set_rate polls for the PLL to lock even if the PLL is > disabled. However, if the PLL is disabled then LOCK_DET will never > assert and we'll return an error. There is no reason to poll LOCK_DET > if the PLL is already disabled, so skip polling in this case. Two separate commits, missing Fixes tags. > > Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> > --- > drivers/clk/qcom/clk-alpha-pll.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 6107c144c0f5..d2bef078588f 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -2061,6 +2061,18 @@ static void clk_zonda_pll_disable(struct clk_hw *hw) regmap_write(regmap, PLL_OPMODE(pll), 0x0); } +static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l) +{ + u64 remainder, quotient; + + quotient = rate; + remainder = do_div(quotient, prate); + *l = quotient; + + if ((remainder * 2) / prate) + *l = *l + 1; +} + static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { @@ -2077,9 +2089,15 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, if (ret < 0) return ret; + if (a & BIT(15)) + zonda_pll_adjust_l_val(rate, prate, &l); + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); + if (!clk_hw_is_enabled(hw)) + return 0; + /* Wait before polling for the frequency latch */ udelay(5);
The Zonda PLL has a 16 bit signed alpha and in the cases where the alpha value is greater than 0.5, the L value needs to be adjusted accordingly. Thus update the logic for the same. Also, fix zonda set_rate failure when PLL is disabled. Currently, clk_zonda_pll_set_rate polls for the PLL to lock even if the PLL is disabled. However, if the PLL is disabled then LOCK_DET will never assert and we'll return an error. There is no reason to poll LOCK_DET if the PLL is already disabled, so skip polling in this case. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> --- drivers/clk/qcom/clk-alpha-pll.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)