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Tue, 9 Jul 2024 15:10:28 GMT Received: from tengfan-gv.ap.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 9 Jul 2024 08:10:19 -0700 From: Tengfei Fan Date: Tue, 9 Jul 2024 23:10:07 +0800 Subject: [PATCH v2 1/2] dt-bindings: clock: qcom: describe the GPUCC clock for QCS9100 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240709-add_qcs9100_gpucc_compatible-v2-1-c206bccc495b@quicinc.com> References: <20240709-add_qcs9100_gpucc_compatible-v2-0-c206bccc495b@quicinc.com> In-Reply-To: <20240709-add_qcs9100_gpucc_compatible-v2-0-c206bccc495b@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das CC: , , , , , Tengfei Fan X-Mailer: b4 0.15-dev-a66ce X-Developer-Signature: v=1; a=ed25519-sha256; t=1720537816; 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It matches the generic QCom GPUCC description. Add device-specific DT bindings defines as well. QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p platform use non-SCMI resource. In the future, the SA8775p platform will move to use SCMI resources and it will have new sa8775p-related device tree. Consequently, introduce "qcom,qcs9100-gpucc" to describe non-SCMI based GPUCC clock. Signed-off-by: Tengfei Fan --- Documentation/devicetree/bindings/clock/qcom,gpucc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index 0858fd635282..33eb62ec4745 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -27,6 +27,7 @@ description: | properties: compatible: enum: + - qcom,qcs9100-gpucc - qcom,sdm845-gpucc - qcom,sa8775p-gpucc - qcom,sc7180-gpucc