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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-594bd45a162sm2204844a12.68.2024.07.10.06.29.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jul 2024 06:29:16 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 10 Jul 2024 14:29:15 +0100 Subject: [PATCH v3 2/2] clk: samsung: gs101: don't mark non-essential (UART) clocks critical Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240710-gs101-non-essential-clocks-2-v3-2-5dcb8d040d1c@linaro.org> References: <20240710-gs101-non-essential-clocks-2-v3-0-5dcb8d040d1c@linaro.org> In-Reply-To: <20240710-gs101-non-essential-clocks-2-v3-0-5dcb8d040d1c@linaro.org> To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Sam Protsenko , Tudor Ambarus Cc: Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, =?utf-8?q?An?= =?utf-8?q?dr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 The peric0_top1_ipclk_0 and peric0_top1_pclk_0 are the clocks going to peric0/uart_usi, with pclk being the bus clock. Without pclk running, any bus access will hang. Unfortunately, in commit d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") the gs101 DT ended up specifying an incorrect pclk in the respective node and instead the two clocks here were marked as critical. Since then, the DT has been updated to use the correct clock in commit 21e4e8807bfc ("arm64: dts: exynos: gs101: use correct clocks for usi_uart") and the driver here should be corrected and the work-around removed. Note that this commit has the side-effect of causing earlycon to stop to work sometime into the boot for two reasons: * peric0_top1_ipclk_0 requires its parent gout_cmu_peric0_ip to be running, but because earlycon doesn't deal with clocks that parent will be disabled when none of the other drivers that actually deal with clocks correctly require it to be running and the real serial driver (which does deal with clocks) hasn't taken over yet * hand-over between earlycon and serial driver appears to be fragile and clocks get enabled and disabled a few times, which also causes register access to hang while earlycon is still active (A wordier explanation can also be found in [1]) Nonetheless we shouldn't keep these clocks running unconditionally just for earlycon. Clocks should be disabled where possible. If earlycon is required in the future, e.g. for debug, this commit can simply be reverted (locally!). Link: https://lore.kernel.org/all/d45de3b2bb6b48653842cf1f74e58889ed6783ae.camel@linaro.org/ [1] Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0") Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- v3: - add git commit SHA1s (Krzysztof) - add link to wordier description of earlycon issue v2: - commit message typo fixed - collect Reviewed-by: tags --- drivers/clk/samsung/clk-gs101.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c index 85098c61c15e..9769c00b6ca8 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -3946,20 +3946,18 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 21, 0, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical. */ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, 21, CLK_SET_RATE_PARENT, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical. */ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2,