From patchwork Sat Jul 20 12:02:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harry Austen X-Patchwork-Id: 13737818 Received: from mail-4316.protonmail.ch (mail-4316.protonmail.ch [185.70.43.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EB8212D744; Sat, 20 Jul 2024 12:02:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721476932; cv=none; b=WCjcV8udRNbnHM9q4hs/cxPSbJ3kg6IoYXRxBZ7fBZ7X3N7n5F4niYiU+a+bwN3OR0xTZD9J6IG6WjoKG9UWRpLCD7sGPdGZ22QVihWtl9vpdganRdz2wfycHrpVRoELoC66dO5W7O6C1qqXZXa9dHmwavdp9BQjoiW3UBThPQ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721476932; c=relaxed/simple; bh=Ws4IVpy523pqF5J7VdsVTx/0uNjG4GIOrUTuGNPVRoo=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YXTdZkk3SB3nDy3OXQ3qMfEWShEyRuby6SjfQfh9rXMypD5MEJ/Ywfju804zy38JPYjjc5h4NOdN5Gwqm6R/qVJTBIFW4Xt5cgcnVXDzuV34s1gbFCuoIAY2OVBvBzpMaHkJ94a1QeooSJ8tlwzzTW4G7Q0yMqL3jWrLDVbH8jc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=protonmail.com; spf=pass smtp.mailfrom=protonmail.com; dkim=pass (2048-bit key) header.d=protonmail.com header.i=@protonmail.com header.b=MqlN8s8z; arc=none smtp.client-ip=185.70.43.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=protonmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=protonmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=protonmail.com header.i=@protonmail.com header.b="MqlN8s8z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail3; t=1721476928; x=1721736128; bh=/AxMqXWFPwoh5NZG4M7LLzEizR7UlModDwusasq5CQ0=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=MqlN8s8zAZV40ZxGcDLWi/BAa5SdYTAdLc+NDcwsVX21YNl2MzuK+gmmjhbGDz5q+ CDCDFAd/tan8mAzSsz5GDqlYvwruSS/Nq9gKo0dgE7ll71/XaoVB89fHWFNhFVnFVm 8keS5+xKrSXZ2mffvQ0zg8Im8+UwvaoLJPg3FogiS2SiNPq1SdgjoNcYzMfUsi8lYk o83AWyTvY6mCwadyJBmdouocBB5nsztxtLG4jbpHMe32C05ZjvvpqMIcGViuUIpU7v R3wxxZy+vYqp/n+yuk+fNDEpZbhL3JLDFaJTDHfcBvtvyKieDmWTqndyshGkb5O7O5 i8l1vpcvcuuyg== Date: Sat, 20 Jul 2024 12:02:04 +0000 To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Simek From: Harry Austen Cc: Shubhrajyoti Datta , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Harry Austen Subject: [PATCH 7/7] clk: clocking-wizard: move dynamic reconfig setup behind flag Message-ID: <20240720120048.36758-8-hpausten@protonmail.com> In-Reply-To: <20240720120048.36758-1-hpausten@protonmail.com> References: <20240720120048.36758-1-hpausten@protonmail.com> Feedback-ID: 53116287:user:proton X-Pm-Message-ID: 244be5160229920dc0c841865215c9e04b17831b Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Xilinx clocking wizard IP core's dynamic reconfiguration support is optionally enabled at build time. Use the new boolean devicetree property to indicate whether the hardware supports this feature or not. Signed-off-by: Harry Austen --- drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 87 +++++++++++----------- 1 file changed, 45 insertions(+), 42 deletions(-) diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c index 2d419e8ad4419..8efe5246c8c0d 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -1185,20 +1185,6 @@ static int clk_wzrd_probe(struct platform_device *pdev) if (IS_ERR(clk_wzrd->base)) return PTR_ERR(clk_wzrd->base); - ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade); - if (!ret) { - if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) { - dev_warn(&pdev->dev, "invalid speed grade '%d'\n", - clk_wzrd->speed_grade); - clk_wzrd->speed_grade = 0; - } - } - - clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1"); - if (IS_ERR(clk_wzrd->clk_in1)) - return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1), - "clk_in1 not found\n"); - clk_wzrd->axi_clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk"); if (IS_ERR(clk_wzrd->axi_clk)) return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk), @@ -1220,40 +1206,57 @@ static int clk_wzrd_probe(struct platform_device *pdev) } } - ret = of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs); - if (ret || nr_outputs > WZRD_NUM_OUTPUTS) - return -EINVAL; - - clk_wzrd->clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_wzrd->clk_data, hws, - nr_outputs), GFP_KERNEL); - if (!clk_wzrd->clk_data) - return -ENOMEM; + if (of_property_read_bool(np, "xlnx,dynamic-reconfig")) { + ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade); + if (!ret) { + if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) { + dev_warn(&pdev->dev, "invalid speed grade '%d'\n", + clk_wzrd->speed_grade); + clk_wzrd->speed_grade = 0; + } + } - ret = clk_wzrd_register_output_clocks(&pdev->dev, nr_outputs); - if (ret) - return ret; + clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1"); + if (IS_ERR(clk_wzrd->clk_in1)) + return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1), + "clk_in1 not found\n"); - clk_wzrd->clk_data->num = nr_outputs; - ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, clk_wzrd->clk_data); - if (ret) { - dev_err(&pdev->dev, "unable to register clock provider\n"); - return ret; - } + ret = of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs); + if (ret || nr_outputs > WZRD_NUM_OUTPUTS) + return -EINVAL; - if (clk_wzrd->speed_grade) { - clk_wzrd->nb.notifier_call = clk_wzrd_clk_notifier; + clk_wzrd->clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_wzrd->clk_data, hws, + nr_outputs), GFP_KERNEL); + if (!clk_wzrd->clk_data) + return -ENOMEM; - ret = devm_clk_notifier_register(&pdev->dev, clk_wzrd->clk_in1, - &clk_wzrd->nb); + ret = clk_wzrd_register_output_clocks(&pdev->dev, nr_outputs); if (ret) - dev_warn(&pdev->dev, - "unable to register clock notifier\n"); + return ret; + + clk_wzrd->clk_data->num = nr_outputs; + ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, + clk_wzrd->clk_data); + if (ret) { + dev_err(&pdev->dev, "unable to register clock provider\n"); + return ret; + } - ret = devm_clk_notifier_register(&pdev->dev, clk_wzrd->axi_clk, - &clk_wzrd->nb); - if (ret) - dev_warn(&pdev->dev, - "unable to register clock notifier\n"); + if (clk_wzrd->speed_grade) { + clk_wzrd->nb.notifier_call = clk_wzrd_clk_notifier; + + ret = devm_clk_notifier_register(&pdev->dev, clk_wzrd->clk_in1, + &clk_wzrd->nb); + if (ret) + dev_warn(&pdev->dev, + "unable to register clock notifier\n"); + + ret = devm_clk_notifier_register(&pdev->dev, clk_wzrd->axi_clk, + &clk_wzrd->nb); + if (ret) + dev_warn(&pdev->dev, + "unable to register clock notifier\n"); + } } return 0;