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Tue, 30 Jul 2024 08:49:10 +0000 Received: from DB9PR04MB8461.eurprd04.prod.outlook.com ([fe80::b1b9:faa9:901b:c197]) by DB9PR04MB8461.eurprd04.prod.outlook.com ([fe80::b1b9:faa9:901b:c197%5]) with mapi id 15.20.7762.020; Tue, 30 Jul 2024 08:49:10 +0000 From: "Peng Fan (OSS)" Date: Tue, 30 Jul 2024 16:57:55 +0800 Subject: [PATCH v3 2/2] clk: clk-conf: support assigned-clock-rates-u64 Message-Id: <20240730-clk-u64-v3-2-4d2b19edaa6e@nxp.com> References: <20240730-clk-u64-v3-0-4d2b19edaa6e@nxp.com> In-Reply-To: <20240730-clk-u64-v3-0-4d2b19edaa6e@nxp.com> To: Rob Herring , Saravana Kannan , Michael Turquette , Stephen Boyd , Luca Ceresoli Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Peng Fan X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1722329887; l=2412; i=peng.fan@nxp.com; s=20230812; h=from:subject:message-id; bh=J5oFMdGnIXFx9n/65+BOh2zj6XyKbv53dEmcaGstyuI=; b=UhMJbV25O1exKMZCzyHLn3ZwXPY4PneE5qvA4s5rfAlHmPku0SN4ZeXrFpebYFQ3ELx8DxqKy IoUKGqJqU++DUVH/olwIPLPZmu2JkH5IbyyHxMKiAdZZuiQVV8BvWwx X-Developer-Key: i=peng.fan@nxp.com; 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So add assigned-clock-rates-u64 support to set rate that exceeds UINT32_MAX. Signed-off-by: Peng Fan --- drivers/clk/clk-conf.c | 42 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c index 058420562020..684e0c0738b3 100644 --- a/drivers/clk/clk-conf.c +++ b/drivers/clk/clk-conf.c @@ -81,11 +81,44 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier) static int __set_clk_rates(struct device_node *node, bool clk_supplier) { struct of_phandle_args clkspec; - int rc, index = 0; + int rc, count, index; struct clk *clk; - u32 rate; + u32 *rates __free(kfree); + bool rate_64 = false; + + count = of_property_count_u64_elems(node, "assigned-clock-rates-u64"); + if (count <= 0) { + count = of_property_count_u32_elems(node, "assigned-clock-rates"); + if (count <= 0) + return 0; + + rates = kcalloc(count, sizeof(u32), GFP_KERNEL); + if (!rates) + return -ENOMEM; + rc = of_property_read_variable_u32_array(node, + "assigned-clock-rates", + rates, + 1, count); + } else { + rates = kcalloc(count, sizeof(u64), GFP_KERNEL); + if (!rates) + return -ENOMEM; + rc = of_property_read_variable_u64_array(node, + "assigned-clock-rates-u64", + (u64 *)rates, + 1, count); + rate_64 = true; + } + + + for (index = 0; index < count; index++) { + unsigned long rate; + + if (rate_64) + rate = ((u64 *)rates)[index]; + else + rate = rates[index]; - of_property_for_each_u32(node, "assigned-clock-rates", rate) { if (rate) { rc = of_parse_phandle_with_args(node, "assigned-clocks", "#clock-cells", index, &clkspec); @@ -112,12 +145,11 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier) rc = clk_set_rate(clk, rate); if (rc < 0) - pr_err("clk: couldn't set %s clk rate to %u (%d), current rate: %lu\n", + pr_err("clk: couldn't set %s clk rate to %lu (%d), current rate: %lu\n", __clk_get_name(clk), rate, rc, clk_get_rate(clk)); clk_put(clk); } - index++; } return 0; }