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Fri, 9 Aug 2024 11:55:00 +0000 (GMT) Received: from epsmgmcp1.samsung.com (unknown [182.195.42.82]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20240809115500epsmtrp2c80367f8d87080c5a19cf92e7fb19545~qDVz2GAPg2146221462epsmtrp2X; Fri, 9 Aug 2024 11:55:00 +0000 (GMT) X-AuditID: b6c32a39-8f9ff70000002606-a7-66b6039443c7 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmcp1.samsung.com (Symantec Messaging Gateway) with SMTP id 7F.43.19367.49306B66; Fri, 9 Aug 2024 20:55:00 +0900 (KST) Received: from [127.0.1.1] (unknown [10.113.111.204]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20240809115500epsmtip191c8ab68ce01f1f077dc7530ec32c4d0~qDVzjDugK0371703717epsmtip1h; Fri, 9 Aug 2024 11:55:00 +0000 (GMT) From: Kwanghoon Son Date: Fri, 09 Aug 2024 20:54:12 +0900 Subject: [PATCH v3 1/3] dt-bindings: clock: exynosautov9: add dpum clock Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240809-clk_dpum-v3-1-359decc30fe2@samsung.com> In-Reply-To: <20240809-clk_dpum-v3-0-359decc30fe2@samsung.com> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Chanho Park , Tomasz Figa , Krzysztof Kozlowski Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kwanghoon Son X-Mailer: b4 0.14.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCJsWRmVeSWpSXmKPExsWy7bCmnu4U5m1pBue/alk8mLeNzeLyfm2L NXvPMVlc//Kc1WL+kXOsFr1rrjJZvJx1j83i/PkN7BabHl9jtfjYc4/V4vKuOWwWM87vY7K4 eMrV4v+eHewWh9+0s1r8u7aRxWLVrj+MDoIe72+0snvsnHWX3WPTqk42j81L6j36tqxi9Pi8 SS6ALSrbJiM1MSW1SCE1Lzk/JTMv3VbJOzjeOd7UzMBQ19DSwlxJIS8xN9VWycUnQNctMwfo dCWFssScUqBQQGJxsZK+nU1RfmlJqkJGfnGJrVJqQUpOgWmBXnFibnFpXrpeXmqJlaGBgZEp UGFCdsa1+xeZC44LV/zo7WZuYDzE38XIySEhYCJxedt6RhBbSGAHo8T//yVdjFxA9idGib7J jaxwTsfaZSwwHc29H9kgEjsZJRrXbYeqesUocfDST7BZbALqEkva1rKD2CwCqhLzru4D6xYW 8JC43feRGcTmFRCUODnzCVicWUBeYvvbOVBxW4mfvR/B4pwCdhLHjp0CWyAisJ9Z4tTD52Cr mQVOMEr8ur2AEeImYYnPu9eAJSQETnBILJj6kB0i4SKx+cFRFpiiV8e3QMWlJD6/28sGYWdL HP0IY5dIXJ+1iBXCNpbYv3QyUxcjB9A2TYn1u/QhLuWTePe1hxUkLCHAK9HRJgRhykvc6iyH aBSVOPMUFEIgYQ+JSf91IeEzkVGi/VAj+wRG+VlI3p+F5P1ZCLsWMDKvYhRLLSjOTU8tNiww hcdqcn7uJkZw8tWy3ME4/e0HvUOMTByMhxglOJiVRHibwzelCfGmJFZWpRblxxeV5qQWH2I0 BUbCRGYp0eR8YPrPK4k3NLE0MDEzMjaxMDQzVBLnPXOlLFVIID2xJDU7NbUgtQimj4mDU6qB SSFtTVCq9JPywqN6k3v42npn7f/+6e5Bjja1FM3Unfyno+YZR2vVlbw8Jm5/tHXG1zmqTyc6 mNz3Weaw7gPrSevEJvEN/58uP/9sDruZNa+VANtCr7bc1CJebVvxGeyVXo/1j8Yf/PIqc3LW 9tBCsTr+Jx9L53p91pwZM9c+b/MW8XMGGQ0VRgt4ZX7P9u3ap6sb4e+1qvnH4nvSfbx72WXb DkTJS69Ntzsvffa7suw29frG46/DGOYfPsW4ZPOZZbsK/3/bsOrm/DPnPO13/chQkHadI53w 9EKcoFK2rWt/1RIze/PO07NeMcasDFxiaLBSfZru9yD1+Jar7M01ZhnSHrptmp8jmS/wsagq sRRnJBpqMRcVJwIAjN9AcUcEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplkeLIzCtJLcpLzFFi42LZdlhJTncK87Y0g5VL+SwezNvGZnF5v7bF mr3nmCyuf3nOajH/yDlWi941V5ksXs66x2Zx/vwGdotNj6+xWnzsucdqcXnXHDaLGef3MVlc POVq8X/PDnaLw2/aWS3+XdvIYrFq1x9GB0GP9zda2T12zrrL7rFpVSebx+Yl9R59W1Yxenze JBfAFsVlk5Kak1mWWqRvl8CVce3+ReaC48IVP3q7mRsYD/F3MXJySAiYSDT3fmTrYuTiEBLY zigxa81DdoiEqETH5UbGLkYOIFtY4vDhYoiaF4wS51ongtWwCahLLGlbC2azCKhKzLu6jwXE FhbwkLjd95EZxOYVEJQ4OfMJC8gcZgFNifW79EHCzALyEtvfzoEqsZX42fsRrEQIyD7/hA0k zClgJ3Hs2ClWkLUiAgeZJX6/+cYO4jALnGSUmLhgO9SdwhKfd69hm8AoOAvJulkI62YhWbeA kXkVo2hqQXFuem5ygaFecWJucWleul5yfu4mRnCMaQXtYFy2/q/eIUYmDsZDjBIczEoivM3h m9KEeFMSK6tSi/Lji0pzUosPMUpzsCiJ8yrndKYICaQnlqRmp6YWpBbBZJk4OKUamFbJ1+2r rSp18HU3+5zR2stVqqB2/MkPy7VCvFGXnAT5V099u6V18Q6NjVkX1VTeJdyc0l/sPftg2KPP cz9oC34TfCy1TmJC1e+TrjPkLJpfaeyczt+fsut+hNFK45/7c65cvtsVz8bbNeOl6hGu8gTR a6e3MzvYxlyZurxkueGjvHU+2wwezGfy1oh4yBO8ivsz5+aJc1u/ny+S5nm+ROAD02rWpp28 XfzCnrsmPbkdo83w6cX+IHO2J5k5/gq3rq7MC1ljc3Cbg+y3W3ll57iuB6Xs94/Xm7Ez8dNP 4z05rj/+71s371jfUpmtr1y7u+a+CmCr91HfM1Hw48m0GeJR7qvLd78R3rb+7yJF611KLMUZ iYZazEXFiQBvmRBBIAMAAA== X-CMS-MailID: 20240809115500epcas1p32a698c821765e1a0d5fa998e6e08f1cd X-Msg-Generator: CA CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240809115500epcas1p32a698c821765e1a0d5fa998e6e08f1cd References: <20240809-clk_dpum-v3-0-359decc30fe2@samsung.com> Add dpum clock definitions and compatibles. Also used clock name 'bus' instead of full clock name dout_clkcmu_dpum_bus like other board cmu schema (GS101). Signed-off-by: Kwanghoon Son --- .../bindings/clock/samsung,exynosautov9-clock.yaml | 19 +++++++++++++++++++ include/dt-bindings/clock/samsung,exynosautov9.h | 11 +++++++++++ 2 files changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml index 55c4f94a14d1..32f39e543b36 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml @@ -35,6 +35,7 @@ properties: - samsung,exynosautov9-cmu-top - samsung,exynosautov9-cmu-busmc - samsung,exynosautov9-cmu-core + - samsung,exynosautov9-cmu-dpum - samsung,exynosautov9-cmu-fsys0 - samsung,exynosautov9-cmu-fsys1 - samsung,exynosautov9-cmu-fsys2 @@ -109,6 +110,24 @@ allOf: - const: oscclk - const: dout_clkcmu_core_bus + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-dpum + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: DPU Main bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - if: properties: compatible: diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h index 3065375c2d8b..ce8fb8f7d718 100644 --- a/include/dt-bindings/clock/samsung,exynosautov9.h +++ b/include/dt-bindings/clock/samsung,exynosautov9.h @@ -179,6 +179,17 @@ #define CLK_GOUT_CORE_CCI_PCLK 4 #define CLK_GOUT_CORE_CMU_CORE_PCLK 5 +/* CMU_DPUM */ +#define CLK_MOUT_DPUM_BUS_USER 1 +#define CLK_DOUT_DPUM_BUSP 2 +#define CLK_GOUT_DPUM_ACLK_DECON 3 +#define CLK_GOUT_DPUM_ACLK_DMA 4 +#define CLK_GOUT_DPUM_ACLK_DPP 5 +#define CLK_GOUT_DPUM_SYSMMU_D0_CLK 6 +#define CLK_GOUT_DPUM_SYSMMU_D1_CLK 7 +#define CLK_GOUT_DPUM_SYSMMU_D2_CLK 8 +#define CLK_GOUT_DPUM_SYSMMU_D3_CLK 9 + /* CMU_FSYS0 */ #define CLK_MOUT_FSYS0_BUS_USER 1 #define CLK_MOUT_FSYS0_PCIE_USER 2