| Message ID | 20240816-sa8775p-mm-v3-v1-5-77d53c3c0cef@quicinc.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | Add support for SA8775P Multimedia clock controllers | expand |
On Fri, Aug 16, 2024 at 12:01:47PM +0530, Taniya Das wrote: > Add device tree bindings for the display clock controllers > on Qualcomm SA8775P platform. > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- > .../bindings/clock/qcom,sa8775p-dispcc.yaml | 79 ++++++++++++++++++++ > include/dt-bindings/clock/qcom,sa8775p-dispcc.h | 87 ++++++++++++++++++++++ > 2 files changed, 166 insertions(+) > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 18/08/2024 20:02, Krzysztof Kozlowski wrote: > On Fri, Aug 16, 2024 at 12:01:47PM +0530, Taniya Das wrote: >> Add device tree bindings for the display clock controllers >> on Qualcomm SA8775P platform. >> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> --- >> .../bindings/clock/qcom,sa8775p-dispcc.yaml | 79 ++++++++++++++++++++ >> include/dt-bindings/clock/qcom,sa8775p-dispcc.h | 87 ++++++++++++++++++++++ >> 2 files changed, 166 insertions(+) >> > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Un-reviewed. We achieved consensus allowing sa8775p to stay, but now Qualcomm changes point of view and insists on new approach of dropping sa8775p. Therefore this change does not make much sense in the new approach. Best regards, Krzysztof
On 9/6/2024 5:54 PM, Krzysztof Kozlowski wrote: > On 18/08/2024 20:02, Krzysztof Kozlowski wrote: >> On Fri, Aug 16, 2024 at 12:01:47PM +0530, Taniya Das wrote: >>> Add device tree bindings for the display clock controllers >>> on Qualcomm SA8775P platform. >>> >>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >>> --- >>> .../bindings/clock/qcom,sa8775p-dispcc.yaml | 79 ++++++++++++++++++++ >>> include/dt-bindings/clock/qcom,sa8775p-dispcc.h | 87 ++++++++++++++++++++++ >>> 2 files changed, 166 insertions(+) >>> >> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > Un-reviewed. > > We achieved consensus allowing sa8775p to stay, but now Qualcomm changes > point of view and insists on new approach of dropping sa8775p. Therefore > this change does not make much sense in the new approach. > Krzysztof could you please re-review the patches again? As I understand that Qualcomm will support both SA8775p and QCS9100 in Kernel. There’s no plan to drop SA8775p support. These two SoCs will keep compatible. > Best regards, > Krzysztof >
On 9/13/2024 10:35 AM, Taniya Das wrote: > > > On 9/6/2024 5:54 PM, Krzysztof Kozlowski wrote: >> On 18/08/2024 20:02, Krzysztof Kozlowski wrote: >>> On Fri, Aug 16, 2024 at 12:01:47PM +0530, Taniya Das wrote: >>>> Add device tree bindings for the display clock controllers >>>> on Qualcomm SA8775P platform. >>>> >>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >>>> --- >>>> .../bindings/clock/qcom,sa8775p-dispcc.yaml | 79 >>>> ++++++++++++++++++++ >>>> include/dt-bindings/clock/qcom,sa8775p-dispcc.h | 87 >>>> ++++++++++++++++++++++ >>>> 2 files changed, 166 insertions(+) >>>> >>> >>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> >> Un-reviewed. >> >> We achieved consensus allowing sa8775p to stay, but now Qualcomm changes >> point of view and insists on new approach of dropping sa8775p. Therefore >> this change does not make much sense in the new approach. >> > > Krzysztof could you please re-review the patches again? As I understand > that Qualcomm will support both SA8775p and QCS9100 in Kernel. There’s > no plan to drop SA8775p support. These two SoCs will keep compatible. > Krzysztof, Could you please help reviewing the patches again?
On 04/10/2024 11:31, Taniya Das wrote: > > > On 9/13/2024 10:35 AM, Taniya Das wrote: >> >> >> On 9/6/2024 5:54 PM, Krzysztof Kozlowski wrote: >>> On 18/08/2024 20:02, Krzysztof Kozlowski wrote: >>>> On Fri, Aug 16, 2024 at 12:01:47PM +0530, Taniya Das wrote: >>>>> Add device tree bindings for the display clock controllers >>>>> on Qualcomm SA8775P platform. >>>>> >>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >>>>> --- >>>>> .../bindings/clock/qcom,sa8775p-dispcc.yaml | 79 >>>>> ++++++++++++++++++++ >>>>> include/dt-bindings/clock/qcom,sa8775p-dispcc.h | 87 >>>>> ++++++++++++++++++++++ >>>>> 2 files changed, 166 insertions(+) >>>>> >>>> >>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >>> >>> Un-reviewed. >>> >>> We achieved consensus allowing sa8775p to stay, but now Qualcomm changes >>> point of view and insists on new approach of dropping sa8775p. Therefore >>> this change does not make much sense in the new approach. >>> >> >> Krzysztof could you please re-review the patches again? As I understand >> that Qualcomm will support both SA8775p and QCS9100 in Kernel. There’s >> no plan to drop SA8775p support. These two SoCs will keep compatible. >> > Krzysztof, Could you please help reviewing the patches again? They are not in the patchwork anymore, not in my inbox, so I cannot review them. Please resend. That's generic rule - don't ping needlessly multiple times, but resend. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-dispcc.yaml new file mode 100644 index 000000000000..ce61755e62d4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-dispcc.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on SA8775P + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on SA8775P. + + See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h + +properties: + compatible: + enum: + - qcom,sa8775p-dispcc0 + - qcom,sa8775p-dispcc1 + + clocks: + items: + - description: GCC AHB clock source + - description: Board XO source + - description: Board XO_AO source + - description: Sleep clock source + - description: Link clock from DP0 PHY + - description: VCO DIV clock from DP0 PHY + - description: Link clock from DP1 PHY + - description: VCO DIV clock from DP1 PHY + - description: Byte clock from DSI0 PHY + - description: Pixel clock from DSI0 PHY + - description: Byte clock from DSI1 PHY + - description: Pixel clock from DSI1 PHY + + power-domains: + maxItems: 1 + description: MMCX power domain + +required: + - compatible + - clocks + - power-domains + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/clock/qcom,sa8775p-gcc.h> + clock-controller@af00000 { + compatible = "qcom,sa8775p-dispcc0"; + reg = <0x0af00000 0x20000>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&dp_phy0 0>, + <&dp_phy0 1>, + <&dp_phy1 2>, + <&dp_phy1 3>, + <&dsi_phy0 0>, + <&dsi_phy0 1>, + <&dsi_phy1 2>, + <&dsi_phy1 3>; + power-domains = <&rpmhpd SA8775P_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sa8775p-dispcc.h b/include/dt-bindings/clock/qcom,sa8775p-dispcc.h new file mode 100644 index 000000000000..e2049e510658 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sa8775p-dispcc.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H +#define _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H + +/* DISP_CC_0/1 clocks */ +#define MDSS_DISP_CC_MDSS_AHB1_CLK 0 +#define MDSS_DISP_CC_MDSS_AHB_CLK 1 +#define MDSS_DISP_CC_MDSS_AHB_CLK_SRC 2 +#define MDSS_DISP_CC_MDSS_BYTE0_CLK 3 +#define MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC 4 +#define MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 +#define MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK 6 +#define MDSS_DISP_CC_MDSS_BYTE1_CLK 7 +#define MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC 8 +#define MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 9 +#define MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK 10 +#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK 11 +#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 12 +#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK 13 +#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK_SRC 14 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK 15 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK 23 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC 24 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK 25 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC 26 +#define MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 27 +#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK 28 +#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 29 +#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK 30 +#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK_SRC 31 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK 32 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 33 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 34 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 35 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK 36 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 37 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK 38 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 39 +#define MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 40 +#define MDSS_DISP_CC_MDSS_ESC0_CLK 41 +#define MDSS_DISP_CC_MDSS_ESC0_CLK_SRC 42 +#define MDSS_DISP_CC_MDSS_ESC1_CLK 43 +#define MDSS_DISP_CC_MDSS_ESC1_CLK_SRC 44 +#define MDSS_DISP_CC_MDSS_MDP1_CLK 45 +#define MDSS_DISP_CC_MDSS_MDP_CLK 46 +#define MDSS_DISP_CC_MDSS_MDP_CLK_SRC 47 +#define MDSS_DISP_CC_MDSS_MDP_LUT1_CLK 48 +#define MDSS_DISP_CC_MDSS_MDP_LUT_CLK 49 +#define MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK 50 +#define MDSS_DISP_CC_MDSS_PCLK0_CLK 51 +#define MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC 52 +#define MDSS_DISP_CC_MDSS_PCLK1_CLK 53 +#define MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC 54 +#define MDSS_DISP_CC_MDSS_PLL_LOCK_MONITOR_CLK 55 +#define MDSS_DISP_CC_MDSS_RSCC_AHB_CLK 56 +#define MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK 57 +#define MDSS_DISP_CC_MDSS_VSYNC1_CLK 58 +#define MDSS_DISP_CC_MDSS_VSYNC_CLK 59 +#define MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC 60 +#define MDSS_DISP_CC_PLL0 61 +#define MDSS_DISP_CC_PLL1 62 +#define MDSS_DISP_CC_SLEEP_CLK 63 +#define MDSS_DISP_CC_SLEEP_CLK_SRC 64 +#define MDSS_DISP_CC_SM_OBS_CLK 65 +#define MDSS_DISP_CC_XO_CLK 66 +#define MDSS_DISP_CC_XO_CLK_SRC 67 + +/* DISP_CC_0/1 power domains */ +#define MDSS_DISP_CC_MDSS_CORE_GDSC 0 +#define MDSS_DISP_CC_MDSS_CORE_INT2_GDSC 1 + +/* DISP_CC_0/1 resets */ +#define MDSS_DISP_CC_MDSS_CORE_BCR 0 +#define MDSS_DISP_CC_MDSS_RSCC_BCR 1 + +#endif
Add device tree bindings for the display clock controllers on Qualcomm SA8775P platform. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- .../bindings/clock/qcom,sa8775p-dispcc.yaml | 79 ++++++++++++++++++++ include/dt-bindings/clock/qcom,sa8775p-dispcc.h | 87 ++++++++++++++++++++++ 2 files changed, 166 insertions(+)