From patchwork Mon Aug 26 12:38:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harry Austen X-Patchwork-Id: 13777838 Received: from mail-40131.protonmail.ch (mail-40131.protonmail.ch [185.70.40.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8D56188586; Mon, 26 Aug 2024 12:38:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.40.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724675921; cv=none; b=XN0StyF5GtFNrOpMFh5LyXzKa1ng0LqqSsa2J2/sLy0dRQnndaezBNdZmWK5bL/zuPyUKSvYSb4y2KPpKv35rZPL7VbcO4qz8pzInwmpeIWg1s7MOJwNnyXdu90DLyVuAQShxZT4ozvsuxsjjXncynqGkSJxowrMCjJkqfdyqdQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724675921; c=relaxed/simple; bh=41srDK0MuDn8Elb7xD1mGmMH+Sw4nupfzQfp74UxsXY=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YVgTbATG6Q67s28YPT7k6EWR9YeTzfZkrT7Orvfk5I3z4A0PpXQl0K7AQWByy4UWNPKsXOqY9JEn3DRqd0ekhrMQlFb9Pq6OIR/HbamvHot4DKmNb4KeVIFmd4OBSL2tFU81yEGI8UfqQSOFteXigEkHcObDt2F9mw3MNKJf4EM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=protonmail.com; spf=pass smtp.mailfrom=protonmail.com; dkim=pass (2048-bit key) header.d=protonmail.com header.i=@protonmail.com header.b=kJSvPvHA; arc=none smtp.client-ip=185.70.40.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=protonmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=protonmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=protonmail.com header.i=@protonmail.com header.b="kJSvPvHA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail3; t=1724675917; x=1724935117; bh=h/LZjiViK1KTa6JiCSBo81f43s9SkDGG36Wi8VELnlc=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=kJSvPvHAN9W9tTPypmczzn8CP/pUIs8eoDXoR11bunadPSf/yYUWVjH5qs9ZqurMs eN8LoF5DiCDyvMGpjV23e7OSripcqbsZgUZj8h0pXLq0pfH6Y66BJml4joPJ+BVaiz oqtQDJ91WcAW8YsutLwhMcyaI3c3SBD7h+VCPoTD3ea67eqtTd/Uj4xgqtbj7jKxzw g2K5m+K54Fguhc7hNmvvukyZAZRWrYRA3uqVkp1usOsHUmT/IEIjkgTyGqKl0SsAQH lkS+0JrXP0eU4mkNFyRwejf+2j3I3XSjih+15OYbLBJcE6fVQ7JK8d8PCRhtL8yj7P 7EAvwOzLto5vg== Date: Mon, 26 Aug 2024 12:38:32 +0000 To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Simek , Greg Kroah-Hartman From: Harry Austen Cc: Shubhrajyoti Datta , Dave Ertman , Ira Weiny , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Harry Austen Subject: [PATCH v3 6/9] clk: clocking-wizard: add user clock monitor support Message-ID: <20240826123602.1872-7-hpausten@protonmail.com> In-Reply-To: <20240826123602.1872-1-hpausten@protonmail.com> References: <20240826123602.1872-1-hpausten@protonmail.com> Feedback-ID: 53116287:user:proton X-Pm-Message-ID: c6c0b939de3551c63045bbf6a94385231923af91 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Xilinx clocking wizard IP core supports monitoring of up to four optional user clock inputs, with a corresponding interrupt for notification in change of clock state (stop, underrun, overrun or glitch). Give access to this monitor logic through use of an auxiliary device. Use presence of the user monitor interrupt description in devicetree to indicate whether or not the auxiliary device should be registered. Also, this functionality is only supported from v6.0 onwards, so add indication of support to the device match data, in order to be tied to the utilised compatible string. Signed-off-by: Harry Austen --- drivers/clk/xilinx/Kconfig | 1 + drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 60 ++++++++++++++++++++-- 2 files changed, 56 insertions(+), 5 deletions(-) diff --git a/drivers/clk/xilinx/Kconfig b/drivers/clk/xilinx/Kconfig index 051756953558b..87f507bd9b6f3 100644 --- a/drivers/clk/xilinx/Kconfig +++ b/drivers/clk/xilinx/Kconfig @@ -21,6 +21,7 @@ config COMMON_CLK_XLNX_CLKWZRD tristate "Xilinx Clocking Wizard" depends on OF depends on HAS_IOMEM + select AUXILIARY_BUS help Support for the Xilinx Clocking Wizard IP core clock generator. Adds support for clocking wizard and compatible. diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c index 1a65a7d153c35..35dad2fda254b 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -8,6 +8,7 @@ * */ +#include #include #include #include @@ -129,6 +130,7 @@ enum clk_wzrd_int_clks { * @clks_internal: Internal clocks * @speed_grade: Speed grade of the device * @suspended: Flag indicating power state of the device + * @adev: User clock monitor auxiliary device * @clk_data: Output clock data */ struct clk_wzrd { @@ -139,6 +141,7 @@ struct clk_wzrd { struct clk_hw *clks_internal[wzrd_clk_int_max]; unsigned int speed_grade; bool suspended; + struct auxiliary_device adev; struct clk_hw_onecell_data clk_data; }; @@ -171,8 +174,9 @@ struct clk_wzrd_divider { spinlock_t *lock; /* divider lock */ }; -struct versal_clk_data { +struct clk_wzrd_data { bool is_versal; + bool supports_monitor; }; #define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb) @@ -958,16 +962,58 @@ static int __maybe_unused clk_wzrd_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(clk_wzrd_dev_pm_ops, clk_wzrd_suspend, clk_wzrd_resume); -static const struct versal_clk_data versal_data = { - .is_versal = true, +static const struct clk_wzrd_data version_6_0_data = { + .is_versal = false, + .supports_monitor = true, }; +static const struct clk_wzrd_data versal_data = { + .is_versal = true, + .supports_monitor = true, +}; + +static void clk_wzrd_unregister_adev(void *_adev) +{ + struct auxiliary_device *adev = _adev; + + auxiliary_device_delete(adev); + auxiliary_device_uninit(adev); +} + +static int clk_wzrd_setup_monitor(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct clk_wzrd_data *data = device_get_match_data(dev); + struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev); + struct auxiliary_device *adev = &clk_wzrd->adev; + int ret; + + if (!data || !data->supports_monitor) + return 0; + + adev->name = "clk-mon"; + adev->dev.parent = dev; + adev->dev.platform_data = (__force void *)clk_wzrd->base; + + ret = auxiliary_device_init(adev); + if (ret) + return ret; + + ret = auxiliary_device_add(adev); + if (ret) { + auxiliary_device_uninit(adev); + return ret; + } + + return devm_add_action_or_reset(dev, clk_wzrd_unregister_adev, adev); +} + static int clk_wzrd_register_output_clocks(struct device *dev, int nr_outputs) { const char *clkout_name, *clk_name, *clk_mul_name; struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev); u32 regl, regh, edge, regld, reghd, edged, div; - const struct versal_clk_data *data; + const struct clk_wzrd_data *data; unsigned long flags = 0; bool is_versal = false; void __iomem *ctrl_reg; @@ -1170,6 +1216,10 @@ static int clk_wzrd_probe(struct platform_device *pdev) return -EINVAL; } + ret = clk_wzrd_setup_monitor(pdev); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to setup monitor\n"); + ret = clk_wzrd_register_output_clocks(&pdev->dev, nr_outputs); if (ret) return ret; @@ -1204,7 +1254,7 @@ static const struct of_device_id clk_wzrd_ids[] = { { .compatible = "xlnx,versal-clk-wizard", .data = &versal_data }, { .compatible = "xlnx,clocking-wizard" }, { .compatible = "xlnx,clocking-wizard-v5.2" }, - { .compatible = "xlnx,clocking-wizard-v6.0" }, + { .compatible = "xlnx,clocking-wizard-v6.0", .data = &version_6_0_data }, { }, }; MODULE_DEVICE_TABLE(of, clk_wzrd_ids);