From patchwork Mon Aug 26 12:38:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harry Austen X-Patchwork-Id: 13777839 Received: from mail-40133.protonmail.ch (mail-40133.protonmail.ch [185.70.40.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D17517A5A6 for ; Mon, 26 Aug 2024 12:38:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.40.133 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724675922; cv=none; b=AZuGajGlCXJlmO4I1lomunzEM+JSljd2tY4Or4xvMGYyNvBC72KYQnYrg4RT2lZhfmjR5RiujvIg/dYpptThKH7V/YMHdIDiyN2YIXxxF4j4AwgLiM9FyRCX1loq+6tww98CWOi8Dbse3kugNOVYYwFedlujsAJnn++VoGvWndI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724675922; c=relaxed/simple; bh=lzcURjcSmOthFLoqrPwefiMjLoXk+SnTZKdXF+C63I8=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=r2h1cDL1o/YBJ1+cC9tguts89tQuqCRabsNPql3iDhqAObIMDw6uj9c4NyzKjs4B3m/bajIwDIwjMaxEueIGh0Lc8ejrrYTyumrdXS4qpOIFGdKAPVfQCzKVnwUDFCYit9oS0JlPvzG6bz58a7UIWAo43LX2Gnub92IB9C6joWw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=protonmail.com; spf=pass smtp.mailfrom=protonmail.com; dkim=pass (2048-bit key) header.d=protonmail.com header.i=@protonmail.com header.b=uhm7go/h; arc=none smtp.client-ip=185.70.40.133 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=protonmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=protonmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=protonmail.com header.i=@protonmail.com header.b="uhm7go/h" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail3; t=1724675919; x=1724935119; bh=RBOC+RDywST6N92zvalAllQSujzs0kpTlYmclip8eRc=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=uhm7go/hzA/XiJNo2AAbl0a48N/WIt8x+zhiS3fIUC7+4nXwJFvNkXu3Lrfjp0yVR 7hLeUtok2U4b1rlSCSY66zzP2cRseb2W1LjAhRGDFCJSSxeH0yFyFQocpDSixTAdHO P2f2GWyZlJgahkGWVFxusZt0aNeZSBCoj5U5aeaOu0bdak4scbpTf7LUYqbxlaHZC3 FVLicOxZvcNvubH7IbBjfCrnXxZyTgzemN4zyO6q8qA65VMGaAn6LSwaZ6FrhZ8DiD iL6wRHjaaIh5lLXnv5b8LN1AcjFDKKT2dM491dqi9de3wgRq5+tr8iyz9P/AeGnGng 2+kIPLFnCvquA== Date: Mon, 26 Aug 2024 12:38:36 +0000 To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Simek , Greg Kroah-Hartman From: Harry Austen Cc: Shubhrajyoti Datta , Dave Ertman , Ira Weiny , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Harry Austen Subject: [PATCH v3 7/9] uio: add Xilinx user clock monitor support Message-ID: <20240826123602.1872-8-hpausten@protonmail.com> In-Reply-To: <20240826123602.1872-1-hpausten@protonmail.com> References: <20240826123602.1872-1-hpausten@protonmail.com> Feedback-ID: 53116287:user:proton X-Pm-Message-ID: e5939776709711e659ff91bcb8ce68658111b277 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Xilinx clocking wizard IP core supports monitoring of up to four optional user clock inputs, with a corresponding interrupt for notification in change of clock state (stop, underrun, overrun or glitch). Give userspace access to this monitor logic through use of the UIO framework. Implemented as an auxiliary_driver to avoid introducing UIO dependency to the main clock driver. Signed-off-by: Harry Austen --- drivers/uio/Kconfig | 8 ++++ drivers/uio/Makefile | 1 + drivers/uio/uio_xlnx_clk_mon.c | 71 ++++++++++++++++++++++++++++++++++ 3 files changed, 80 insertions(+) create mode 100644 drivers/uio/uio_xlnx_clk_mon.c diff --git a/drivers/uio/Kconfig b/drivers/uio/Kconfig index b060dcd7c6350..ca8a53de26a67 100644 --- a/drivers/uio/Kconfig +++ b/drivers/uio/Kconfig @@ -164,4 +164,12 @@ config UIO_DFL opae-sdk/tools/libopaeuio/ If you compile this as a module, it will be called uio_dfl. + +config UIO_XLNX_CLK_MON + tristate "Xilinx user clock monitor support" + depends on COMMON_CLK_XLNX_CLKWZRD + help + Userspace I/O interface to the user clock monitor logic within the + Xilinx Clocking Wizard IP core. + endif diff --git a/drivers/uio/Makefile b/drivers/uio/Makefile index 1c5f3b5a95cf5..1e8c242265431 100644 --- a/drivers/uio/Makefile +++ b/drivers/uio/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_UIO_MF624) += uio_mf624.o obj-$(CONFIG_UIO_FSL_ELBC_GPCM) += uio_fsl_elbc_gpcm.o obj-$(CONFIG_UIO_HV_GENERIC) += uio_hv_generic.o obj-$(CONFIG_UIO_DFL) += uio_dfl.o +obj-$(CONFIG_UIO_XLNX_CLK_MON) += uio_xlnx_clk_mon.o diff --git a/drivers/uio/uio_xlnx_clk_mon.c b/drivers/uio/uio_xlnx_clk_mon.c new file mode 100644 index 0000000000000..afcbeae98eaaf --- /dev/null +++ b/drivers/uio/uio_xlnx_clk_mon.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for user clock monitor logic within Xilinx 'Clocking Wizard' IP core + * + * Copyright (C) 2024 Harry Austen + */ + +#include +#include +#include +#include +#include +#include + +#define WZRD_INTR_ENABLE 0x10 + +static int clk_mon_irqcontrol(struct uio_info *info, s32 irq_on) +{ + if (irq_on) + iowrite32(GENMASK(15, 0), info->mem[0].internal_addr + WZRD_INTR_ENABLE); + else + iowrite32(0, info->mem[0].internal_addr + WZRD_INTR_ENABLE); + + return 0; +} + +static int probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id) +{ + struct platform_device *pdev = to_platform_device(adev->dev.parent); + struct device *dev = &adev->dev; + struct uio_info *info; + int irq; + + info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return 0; + + info->name = KBUILD_MODNAME; + info->version = "0.0.1"; + + info->mem[0].name = "clock monitor"; + info->mem[0].memtype = UIO_MEM_PHYS; + info->mem[0].addr = platform_get_resource(pdev, IORESOURCE_IO, 0)->start; + info->mem[0].size = (WZRD_INTR_ENABLE + 4 + PAGE_SIZE - 1) & PAGE_MASK; + info->mem[0].internal_addr = (__force void __iomem *)dev->platform_data; + + info->irq = irq; + info->irqcontrol = clk_mon_irqcontrol; + return devm_uio_register_device(dev, info); +} + +static struct auxiliary_device_id ids[] = { + { .name = "clk_xlnx_clock_wizard.clk-mon" }, + {} +}; +MODULE_DEVICE_TABLE(auxiliary, ids); + +static struct auxiliary_driver xlnx_clk_mon_driver = { + .id_table = ids, + .probe = probe, +}; + +module_auxiliary_driver(xlnx_clk_mon_driver); + +MODULE_AUTHOR("Harry Austen "); +MODULE_DESCRIPTION("Driver for Xilinx user clock monitor logic"); +MODULE_LICENSE("GPL");