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Tue, 27 Aug 2024 12:46:31 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 27 Aug 2024 05:46:26 -0700 From: Luo Jie Date: Tue, 27 Aug 2024 20:46:01 +0800 Subject: [PATCH v3 3/4] arm64: defconfig: Enable Qualcomm IPQ CMN PLL clock controller Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240827-qcom_ipq_cmnpll-v3-3-8e009cece8b2@quicinc.com> References: <20240827-qcom_ipq_cmnpll-v3-0-8e009cece8b2@quicinc.com> In-Reply-To: <20240827-qcom_ipq_cmnpll-v3-0-8e009cece8b2@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , , , Luo Jie , Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724762769; l=1117; i=quic_luoj@quicinc.com; s=20240808; h=from:subject:message-id; bh=UaJZoPaUKYUb0JNe2CasqNamoyffxUmH95LhSH+Qa6M=; b=VVSnrjL0qWG+Gq9IuZLdGXAQ3CxPj/o2zTGozeddVsCtFR6+QTp8IOoIhsX7B2Rkk7M345HrY Il2hyHtSm/IDSeXcn1Y/hhDcWL+1YYEG0QfGMngosRQuAyZmzYSFslm X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=P81jeEL23FcOkZtXZXeDDiPwIwgAHVZFASJV12w3U6w= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ENwcUfHRXbCVDRm17U-EcOetv5auUMLO X-Proofpoint-GUID: ENwcUfHRXbCVDRm17U-EcOetv5auUMLO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-27_06,2024-08-27_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 malwarescore=0 impostorscore=0 clxscore=1015 adultscore=0 suspectscore=0 mlxscore=0 mlxlogscore=783 spamscore=0 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408270094 The CMN PLL hardware block is available in the Qualcomm IPQ SoC such as IPQ9574 and IPQ5332. It provides fixed rate output clocks to Ethernet related hardware blocks such as external Ethernet PHY or switch. This driver is initially being enabled for IPQ9574. All boards based on IPQ9574 SoC will require to include this driver in the build. This CMN PLL hardware block does not provide any other specific function on the IPQ SoC other than enabling output clocks to Ethernet related devices. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Luo Jie --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 01dd286ba7ef..1bc7bd86e589 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1300,6 +1300,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_APSS_5018=y +CONFIG_IPQ_CMN_PLL=m CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_5332=y CONFIG_IPQ_GCC_6018=y