From patchwork Wed Aug 28 10:15:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13781057 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B97016A934; Wed, 28 Aug 2024 10:15:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724840122; cv=none; b=O9xho7HLTg17fFl9AubGvPxxzvMjxK7nZxH1qK9iZDS+a5yi8AEE3BnOSpYMke9lTr9XcZRB8fhg3GRx735NjsSnRfiQ7cx326GoZYYFmqAqB4oDWgb5MpC9Fcg5lCpE7ZGaoKporJnZWQSapR41vkVdBTQvZ3seLogr55h8+Jc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724840122; c=relaxed/simple; bh=WR14k8P+mLy91L69HY4wBwuOQUnhcX1BRQ5eOt3Bxww=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PPQTusss2bb3urQCWdb2HWAxjOUBb7bCQMGvqnmZu+o1jQ9qd1HRyCmML4XXTlBpdAbpk6HvwwF0LmBMoEa1GeHzDSK81FpPsu3ZxkAdCniWEY/NLKc7PkvhF37ckIlkMe5aF2owxVUWdCf7NeHEOzkk/qMb1WI0bLV1TgnOPjM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=Wxv9aYnC; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="Wxv9aYnC" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=PlRpVtIBwwyT7sJiOXWleLS+M54tw81jUNBu+u7QyPQ=; b=Wxv9aYnCBQ2sHWb4hEkwzkky2w hMLxucWM2eLIQdW66oKCOAmlzru8RSS20sw7pDv8j/rjhg6zImCqeAV+yBgf8MZbiz/a/q17KkNxz 2B9HDDosW7MzfH/FqEyzAciSIuXYOMl8RJBXt9TzbCHHzedUkg5+HKu1SfyGbjQoilXlBqGjSdZpk mFjDi7xv0rYs3PiYhwTk4Z1uQD5/XA+N0XIMJJNRb943XBGuxrpWoBIl2f1U2oWXxvaPwNtxz5hUt MoG0VhPdI+SmoEUSyGLPaOB4r63sC/3pr2OhRpH3ylvcbq7Qbk/tAdKbdHqmzb4rUvDIHh7F0/ZqW KYd0eVow==; Received: from i5e8616cd.versanet.de ([94.134.22.205] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1sjFhu-0004M3-7X; Wed, 28 Aug 2024 12:15:18 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-clk@vger.kernel.org, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v3 5/5] arm64: dts: rockchip: fix the pcie refclock oscillator on Rock 5 ITX Date: Wed, 28 Aug 2024 12:15:03 +0200 Message-ID: <20240828101503.1478491-6-heiko@sntech.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240828101503.1478491-1-heiko@sntech.de> References: <20240828101503.1478491-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Rock 5 ITX uses two PCIe controllers to drive both a M.2 slot and its SATA controller with 2 lanes each. The supply for the refclk oscillator is the same that supplies the M.2 slot, but the SATA controller port is supplied by a different rail. This leads to the effect that if the PCIe30x4 controller for the M.2 probes first, everything works normally. But if the PCIe30x2 controller that is connected to the SATA controller probes first, it will hang on the first DBI read as nothing will have enabled the refclock before. Fix this by describing the clock generator with its supplies so that both controllers can reference it as needed. Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-rock-5-itx.dts | 38 ++++++++++++++++++- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts index d0b922b8d67e..2d0bcf90bf0f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -72,6 +72,15 @@ hdd-led2 { }; }; + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ + pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_05>; + }; + fan0: pwm-fan { compatible = "pwm-fan"; #cooling-cells = <2>; @@ -146,13 +155,14 @@ vcc3v3_lan: vcc3v3_lan_phy2: regulator-vcc3v3-lan { vin-supply = <&vcc_3v3_s3>; }; - vcc3v3_mkey: regulator-vcc3v3-mkey { + /* The PCIE30x4_PWREN_H controls two regulators */ + vcc3v3_mkey: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { compatible = "regulator-fixed"; enable-active-high; gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie30x4_pwren_h>; - regulator-name = "vcc3v3_mkey"; + regulator-name = "vcc3v3_pi6c_05"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; startup-delay-us = <5000>; @@ -513,6 +523,18 @@ &pcie30phy { /* ASMedia ASM1164 Sata controller */ &pcie3x2 { + /* + * The board has a "pcie_refclk" oscillator that needs enabling, + * so add it to the list of clocks. + */ + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>, + <&pcie30_port1_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2_perstn_m1_l>; reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; @@ -522,6 +544,18 @@ &pcie3x2 { /* M.2 M.key */ &pcie3x4 { + /* + * The board has a "pcie_refclk" oscillator that needs enabling, + * so add it to the list of clocks. + */ + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, + <&pcie30_port0_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; num-lanes = <2>; pinctrl-names = "default"; pinctrl-0 = <&pcie30x4_perstn_m1_l>;