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([82.78.167.144]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42ba642594dsm80361785e9.47.2024.08.30.06.02.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 06:02:34 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Subject: [PATCH v3 02/12] dt-bindings: clock: r9a08g045-vbattb: Add clock IDs for the VBATTB controller Date: Fri, 30 Aug 2024 16:02:08 +0300 Message-Id: <20240830130218.3377060-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240830130218.3377060-1-claudiu.beznea.uj@bp.renesas.com> References: <20240830130218.3377060-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The VBATTB controllers controls the clock for the RTC on the Renesas RZ/G3S. The HW block diagram for the clock logic is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ ,/ One could connect as input to this HW block either a crystal oscillator or an external clock device. After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: input-xtal xbyp xc mux vbattclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. This allows select the input of the mux based on the type of the connected input clock: - if the 32768 crystal oscillator is connected as input for the VBATTB, the input of the mux should be xc - if an external clock device is connected as input for the VBATTB the input of the mux should be xbyp Add clock IDs for the VBATTB controller. Signed-off-by: Claudiu Beznea --- Changes in v3: - none; this patch is new include/dt-bindings/clock/r9a08g045-vbattb.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 include/dt-bindings/clock/r9a08g045-vbattb.h diff --git a/include/dt-bindings/clock/r9a08g045-vbattb.h b/include/dt-bindings/clock/r9a08g045-vbattb.h new file mode 100644 index 000000000000..67774eafad06 --- /dev/null +++ b/include/dt-bindings/clock/r9a08g045-vbattb.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ +#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ + +#define VBATTB_XC 0 +#define VBATTB_XBYP 1 +#define VBATTB_MUX 2 +#define VBATTB_VBATTCLK 3 + +#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */