| Message ID | 20240831-clk-en7581-syscon-v1-4-5c2683541068@kernel.org (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | clk: en7523: Update register mapping for EN7581 | expand |
Hi Lorenzo,
kernel test robot noticed the following build warnings:
url: https://github.com/intel-lab-lkp/linux/commits/Lorenzo-Bianconi/dt-bindings-clock-airoha-update-reg-mapping-for-EN7581-SoC/20240831-152135
base: f0e992956eb617c8f16119944bfe101dea074147
patch link: https://lore.kernel.org/r/20240831-clk-en7581-syscon-v1-4-5c2683541068%40kernel.org
patch subject: [PATCH 4/7] clk: en7523: introduce chip_scu regmap
config: nios2-randconfig-r072-20240902 (https://download.01.org/0day-ci/archive/20240902/202409021114.11d1W3PJ-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 14.1.0
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202409021114.11d1W3PJ-lkp@intel.com/
New smatch warnings:
drivers/clk/clk-en7523.c:471 en7581_register_clocks() error: uninitialized symbol 'hw'.
drivers/clk/clk-en7523.c:471 en7581_register_clocks() warn: passing zero to 'PTR_ERR'
Old smatch warnings:
drivers/clk/clk-en7523.c:478 en7581_register_clocks() error: uninitialized symbol 'hw'.
drivers/clk/clk-en7523.c:478 en7581_register_clocks() warn: passing zero to 'PTR_ERR'
vim +/hw +471 drivers/clk/clk-en7523.c
f114fc7e44857f Lorenzo Bianconi 2024-08-31 459 static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
f114fc7e44857f Lorenzo Bianconi 2024-08-31 460 struct regmap *map, void __iomem *base)
f114fc7e44857f Lorenzo Bianconi 2024-08-31 461 {
f114fc7e44857f Lorenzo Bianconi 2024-08-31 462 struct clk_hw *hw;
f114fc7e44857f Lorenzo Bianconi 2024-08-31 463 u32 rate;
f114fc7e44857f Lorenzo Bianconi 2024-08-31 464 int i;
f114fc7e44857f Lorenzo Bianconi 2024-08-31 465
f114fc7e44857f Lorenzo Bianconi 2024-08-31 466 for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {
f114fc7e44857f Lorenzo Bianconi 2024-08-31 467 const struct en_clk_desc *desc = &en7523_base_clks[i];
f114fc7e44857f Lorenzo Bianconi 2024-08-31 468 u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg;
f114fc7e44857f Lorenzo Bianconi 2024-08-31 469
f114fc7e44857f Lorenzo Bianconi 2024-08-31 470 if (regmap_read(map, desc->base_reg, &val)) {
f114fc7e44857f Lorenzo Bianconi 2024-08-31 @471 pr_err("Failed reading fixed clk rate %s: %ld\n",
f114fc7e44857f Lorenzo Bianconi 2024-08-31 472 desc->name, PTR_ERR(hw));
^^
Uninitialized
f114fc7e44857f Lorenzo Bianconi 2024-08-31 473 continue;
f114fc7e44857f Lorenzo Bianconi 2024-08-31 474 }
f114fc7e44857f Lorenzo Bianconi 2024-08-31 475 rate = en7523_get_base_rate(desc, val);
f114fc7e44857f Lorenzo Bianconi 2024-08-31 476
f114fc7e44857f Lorenzo Bianconi 2024-08-31 477 if (regmap_read(map, reg, &val)) {
f114fc7e44857f Lorenzo Bianconi 2024-08-31 478 pr_err("Failed reading fixed clk div %s: %ld\n",
f114fc7e44857f Lorenzo Bianconi 2024-08-31 479 desc->name, PTR_ERR(hw));
^^
Uniniitialized
f114fc7e44857f Lorenzo Bianconi 2024-08-31 480 continue;
f114fc7e44857f Lorenzo Bianconi 2024-08-31 481 }
f114fc7e44857f Lorenzo Bianconi 2024-08-31 482 rate /= en7523_get_div(desc, val);
f114fc7e44857f Lorenzo Bianconi 2024-08-31 483
f114fc7e44857f Lorenzo Bianconi 2024-08-31 484 hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate);
f114fc7e44857f Lorenzo Bianconi 2024-08-31 485 if (IS_ERR(hw)) {
f114fc7e44857f Lorenzo Bianconi 2024-08-31 486 pr_err("Failed to register clk %s: %ld\n",
f114fc7e44857f Lorenzo Bianconi 2024-08-31 487 desc->name, PTR_ERR(hw));
f114fc7e44857f Lorenzo Bianconi 2024-08-31 488 continue;
f114fc7e44857f Lorenzo Bianconi 2024-08-31 489 }
f114fc7e44857f Lorenzo Bianconi 2024-08-31 490
f114fc7e44857f Lorenzo Bianconi 2024-08-31 491 clk_data->hws[desc->id] = hw;
f114fc7e44857f Lorenzo Bianconi 2024-08-31 492 }
f114fc7e44857f Lorenzo Bianconi 2024-08-31 493
f114fc7e44857f Lorenzo Bianconi 2024-08-31 494 hw = en7523_register_pcie_clk(dev, base);
f114fc7e44857f Lorenzo Bianconi 2024-08-31 495 clk_data->hws[EN7523_CLK_PCIE] = hw;
f114fc7e44857f Lorenzo Bianconi 2024-08-31 496
f114fc7e44857f Lorenzo Bianconi 2024-08-31 497 clk_data->num = EN7523_NUM_CLOCKS;
f114fc7e44857f Lorenzo Bianconi 2024-08-31 498 }
diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 78bcb0ce77a5..d0f936ec6bb2 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -255,15 +255,11 @@ static const u16 en7581_rst_map[] = { [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31, }; -static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) +static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val) { - const struct en_clk_desc *desc = &en7523_base_clks[i]; - u32 val; - if (!desc->base_bits) return desc->base_value; - val = readl(base + desc->base_reg); val >>= desc->base_shift; val &= (1 << desc->base_bits) - 1; @@ -273,16 +269,11 @@ static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) return desc->base_values[val]; } -static u32 en7523_get_div(void __iomem *base, int i) +static u32 en7523_get_div(const struct en_clk_desc *desc, u32 val) { - const struct en_clk_desc *desc = &en7523_base_clks[i]; - u32 reg, val; - if (!desc->div_bits) return 1; - reg = desc->div_reg ? desc->div_reg : desc->base_reg; - val = readl(base + reg); val >>= desc->div_shift; val &= (1 << desc->div_bits) - 1; @@ -424,9 +415,12 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg; + u32 val = readl(base + desc->base_reg); - rate = en7523_get_base_rate(base, i); - rate /= en7523_get_div(base, i); + rate = en7523_get_base_rate(desc, val); + val = readl(base + reg); + rate /= en7523_get_div(desc, val); hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); if (IS_ERR(hw)) { @@ -462,22 +456,63 @@ static int en7523_clk_hw_init(struct platform_device *pdev, return 0; } +static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, + struct regmap *map, void __iomem *base) +{ + struct clk_hw *hw; + u32 rate; + int i; + + for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { + const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; + + if (regmap_read(map, desc->base_reg, &val)) { + pr_err("Failed reading fixed clk rate %s: %ld\n", + desc->name, PTR_ERR(hw)); + continue; + } + rate = en7523_get_base_rate(desc, val); + + if (regmap_read(map, reg, &val)) { + pr_err("Failed reading fixed clk div %s: %ld\n", + desc->name, PTR_ERR(hw)); + continue; + } + rate /= en7523_get_div(desc, val); + + hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); + if (IS_ERR(hw)) { + pr_err("Failed to register clk %s: %ld\n", + desc->name, PTR_ERR(hw)); + continue; + } + + clk_data->hws[desc->id] = hw; + } + + hw = en7523_register_pcie_clk(dev, base); + clk_data->hws[EN7523_CLK_PCIE] = hw; + + clk_data->num = EN7523_NUM_CLOCKS; +} + static int en7581_clk_hw_init(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data) { - void __iomem *base, *np_base; + void __iomem *np_base; struct regmap *map; u32 val; - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); + if (IS_ERR(map)) + return PTR_ERR(map); - np_base = devm_platform_ioremap_resource(pdev, 1); + np_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(np_base)) return PTR_ERR(np_base); - en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + en7581_register_clocks(&pdev->dev, clk_data, map, np_base); val = readl(np_base + REG_NP_SCU_SSTR); val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); @@ -565,7 +600,7 @@ static int en7523_reset_register(struct platform_device *pdev, if (!soc_data->reset.idx_map_nr) return 0; - base = devm_platform_ioremap_resource(pdev, 2); + base = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(base)) return PTR_ERR(base);
Introduce chip_scu regmap pointer since EN7581 SoC will access chip-scu memory area through a syscon node. Remove first memory region mapping for EN7581 SoC. This patch does not introduce any backward incompatibility since the dts for EN7581 SoC is not public yet. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> --- drivers/clk/clk-en7523.c | 75 +++++++++++++++++++++++++++++++++++------------- 1 file changed, 55 insertions(+), 20 deletions(-)