| Message ID | 20240906-fix_clk-v1-3-2977ef0d72e7@amlogic.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: meson: Fix an issue with inaccurate hifi_pll frequency | expand |
On Fri 06 Sep 2024 at 13:52, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org> wrote: > From: Chuan Liu <chuan.liu@amlogic.com> > > The s4's hifi_pll supports a fractional frequency multiplier, but frac > parameters are not configured in the driver. That should probably have been sent separately. It's about frac, yes, but it has nothing to do with the issue described in the cover letter. > > Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> > --- > drivers/clk/meson/s4-pll.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c > index b0258933fb9d..a97e19057b05 100644 > --- a/drivers/clk/meson/s4-pll.c > +++ b/drivers/clk/meson/s4-pll.c > @@ -329,7 +329,6 @@ static struct clk_regmap s4_gp0_pll = { > * Internal hifi pll emulation configuration parameters > */ > static const struct reg_sequence s4_hifi_init_regs[] = { > - { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00010e56 }, > { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 }, > { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 }, > { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 }, > @@ -354,6 +353,11 @@ static struct clk_regmap s4_hifi_pll_dco = { > .shift = 10, > .width = 5, > }, > + .frac = { > + .reg_off = ANACTRL_HIFIPLL_CTRL1, > + .shift = 0, > + .width = 17, > + }, > .l = { > .reg_off = ANACTRL_HIFIPLL_CTRL0, > .shift = 31,
diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c index b0258933fb9d..a97e19057b05 100644 --- a/drivers/clk/meson/s4-pll.c +++ b/drivers/clk/meson/s4-pll.c @@ -329,7 +329,6 @@ static struct clk_regmap s4_gp0_pll = { * Internal hifi pll emulation configuration parameters */ static const struct reg_sequence s4_hifi_init_regs[] = { - { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00010e56 }, { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 }, { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 }, { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 }, @@ -354,6 +353,11 @@ static struct clk_regmap s4_hifi_pll_dco = { .shift = 10, .width = 5, }, + .frac = { + .reg_off = ANACTRL_HIFIPLL_CTRL1, + .shift = 0, + .width = 17, + }, .l = { .reg_off = ANACTRL_HIFIPLL_CTRL0, .shift = 31,