From patchwork Sat Sep 14 05:25:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 13804200 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBF3225570; Sat, 14 Sep 2024 05:25:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726291532; cv=none; b=f+nvQqgwhymYL/pryj4lONZgcW7JjU02y+/Ed6nD1wsAt8/91k4v+zk4Hb6zHU6aVjn0WxLvkLSb+/CTSFQpxbK/FcRCs0BQXqy6uRGqAc0E+8NT+hLvP2ASmG0qiEsNlZX6Thv7/zOwsYJGGZwNNxSedQtb1iQYRR7kt3iKjqM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726291532; c=relaxed/simple; bh=JFXL0kBIFjySYpsf7icuA3X2ZFh5pKvYLb8OeVi+vM4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NcTLbfWftmmqbCX7skGyTLkIXnQD6DQ0X+61ejLV52RFDH5zIAIovSwpLLPQwc1GG0kz9pBeZpeT1rL2u4Cvjqh8r0z6WNlZ1hbzjjLDUCY53YZsBOvdC/9UM513OUCWLmHE0hyqZB8ZVzvpu2BenSqJiBQ0Xc4VV9phqmVGIpo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=r695Jcj9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="r695Jcj9" Received: by smtp.kernel.org (Postfix) with ESMTPS id 78A9DC4CECE; Sat, 14 Sep 2024 05:25:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1726291532; bh=JFXL0kBIFjySYpsf7icuA3X2ZFh5pKvYLb8OeVi+vM4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=r695Jcj9zH6a9UXm0MJjXmP0PrcHPBoYA0R06h8hnrD8VLMRKmHA5CaCq3HV+ixpO 1pYVw6djM4guJ90RBZSaNckypcFa9hmAYa9krPQbc2sXmxIhH7VG1AZthzQ+jmaRSn dIClF3PH8klnyhaYbVBQJldmvFLGtVhaE+sIOGNcyrnsH4+wAAkhfO4HCwuzwstjlQ fpm0C5mgFFKfoCDk6esDLvkiud8FN+pX/Dyx6W5E8ytW0Ao0hJa1GCx0P3GZiuLXA5 0KG/BLxwyv71U3e6Uv+bCu72H0tSgp7Fi6e4lPz7ZBuC7WsDcBIjFpFO0CLhy3SXEc 6bEM0kdH1Zh3g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67BB9FC6190; Sat, 14 Sep 2024 05:25:32 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Sat, 14 Sep 2024 13:25:24 +0800 Subject: [PATCH 2/5] dt-bindings: clock: add Amlogic A5 SCMI clock controller support Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240914-a5-clk-v1-2-5ee2c4f1b08c@amlogic.com> References: <20240914-a5-clk-v1-0-5ee2c4f1b08c@amlogic.com> In-Reply-To: <20240914-a5-clk-v1-0-5ee2c4f1b08c@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chuan Liu , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726291530; l=1704; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=0VCFX2M/yMc0qFVf2pmxfgH7H6Hn/BYk4VGTASRH4GA=; b=px+kiFx0mdhXES0XOipO96yHeklV9a3/lQKjlLMzizKg/LpwjHRjuxA6w5hmuihPkXCK0Io+t oqr9LBja/8nDeYrshGL6w+md5QIH/yPRJTym02nPg5ceoWGs6sL+TtR X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Chuan Liu Add the SCMI clock controller dt-bindings for Amlogic A5 SoC family. Signed-off-by: Chuan Liu Signed-off-by: Xianwei Zhao Reviewed-by: Rob Herring (Arm) --- include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h new file mode 100644 index 000000000000..d35d1ff6bab3 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef __AMLOGIC_A5_SCMI_CLKC_H +#define __AMLOGIC_A5_SCMI_CLKC_H + +#define CLKID_OSC 0 +#define CLKID_SYS_CLK 1 +#define CLKID_AXI_CLK 2 +#define CLKID_CPU_CLK 3 +#define CLKID_DSU_CLK 4 +#define CLKID_GP1_PLL 5 +#define CLKID_FIXED_PLL_DCO 6 +#define CLKID_FIXED_PLL 7 +#define CLKID_ACLKM 8 +#define CLKID_SYS_PLL_DIV16 9 +#define CLKID_CPU_CLK_DIV16 10 +#define CLKID_FCLK_50M_PREDIV 11 +#define CLKID_FCLK_50M_DIV 12 +#define CLKID_FCLK_50M 13 +#define CLKID_FCLK_DIV2_DIV 14 +#define CLKID_FCLK_DIV2 15 +#define CLKID_FCLK_DIV2P5_DIV 16 +#define CLKID_FCLK_DIV2P5 17 +#define CLKID_FCLK_DIV3_DIV 18 +#define CLKID_FCLK_DIV3 19 +#define CLKID_FCLK_DIV4_DIV 20 +#define CLKID_FCLK_DIV4 21 +#define CLKID_FCLK_DIV5_DIV 22 +#define CLKID_FCLK_DIV5 23 +#define CLKID_FCLK_DIV7_DIV 24 +#define CLKID_FCLK_DIV7 25 + +#endif /* __AMLOGIC_A5_SCMI_CLKC_H */