From patchwork Mon Sep 16 09:10:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Chen X-Patchwork-Id: 13805197 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 723FB1494B2; Mon, 16 Sep 2024 09:10:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726477854; cv=none; b=g3jICQHQhuosJI6Mk2Vgfff71PxcYlQfSWwShdBqXHTXRt/UMrj6imhpvJ4v0SKPeN8eCZR4vv5TE4ORz4uu4V0kqrc53F5wN8NDFySSxM8XoKUsH5vYT4uB665h6j+IGg4KArpGX164q0zZewNIy7xSr4GYrtQND/FuEcl3yXI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726477854; c=relaxed/simple; bh=5aLXonjD9GSwJx49YoGC+aqi7ujgsgmoeaW2LBAUw80=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ChPtfuCFGGSLnuhBSQacZoeRS56JPdoP/8G4/aqs1sR7nNUf7V3um9y8R4oyvVkU+ukyrXBuT5MNHXEnoRBjmpUAgQ1NDZ0x8oy1MULznFMHMLUWaVcr67zQ9PYQ9JeZI7BfYJeCQDwZb2r25unUqunIa6Of33GhBqBKlHHVuGg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 16 Sep 2024 17:10:40 +0800 Received: from twmbx02.aspeed.com (192.168.10.152) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 16 Sep 2024 17:10:40 +0800 From: Ryan Chen To: , , , , , , , , , , , , , Subject: [PATCH v3 1/4] dt-bindings: mfd: aspeed: support for AST2700 Date: Mon, 16 Sep 2024 17:10:36 +0800 Message-ID: <20240916091039.3584505-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916091039.3584505-1-ryan_chen@aspeedtech.com> References: <20240916091039.3584505-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add compatible support for AST2700 clk, reset, pinctrl, silicon-id for AST2700 scu. Signed-off-by: Ryan Chen --- .../devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index 86ee69c0f45b..127a357051cd 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -9,6 +9,8 @@ title: Aspeed System Control Unit description: The Aspeed System Control Unit manages the global behaviour of the SoC, configuring elements such as clocks, pinmux, and reset. + In AST2700 SOC which has two soc connection, each soc have its own scu + register control, ast2700-scu0 for soc0, ast2700-scu1 for soc1. maintainers: - Joel Stanley @@ -21,6 +23,8 @@ properties: - aspeed,ast2400-scu - aspeed,ast2500-scu - aspeed,ast2600-scu + - aspeed,ast2700-scu0 + - aspeed,ast2700-scu1 - const: syscon - const: simple-mfd @@ -30,10 +34,12 @@ properties: ranges: true '#address-cells': - const: 1 + minimum: 1 + maximum: 2 '#size-cells': - const: 1 + minimum: 1 + maximum: 2 '#clock-cells': const: 1 @@ -56,6 +62,8 @@ patternProperties: - aspeed,ast2400-pinctrl - aspeed,ast2500-pinctrl - aspeed,ast2600-pinctrl + - aspeed,ast2700-soc0-pinctrl + - aspeed,ast2700-soc1-pinctrl required: - compatible @@ -76,6 +84,7 @@ patternProperties: - aspeed,ast2400-silicon-id - aspeed,ast2500-silicon-id - aspeed,ast2600-silicon-id + - aspeed,ast2700-silicon-id - const: aspeed,silicon-id reg: