From patchwork Fri Sep 20 10:38:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 13808465 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29B84143888; Fri, 20 Sep 2024 10:38:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726828720; cv=none; b=vBmAH1Y+ybdYTVM6owmWl+s2iOi/qUDOxVL8/G/YpuTo9upeBqtI8bkoQEwnZyaQOnqFuFwtyWy3f6frBWvmCluYskTNxYXPLue/ENfLDwEMENKho+trhz/pTWsaBAC5s3dJlZvN2zU6uTAEgL0fp3XWP+/gyvcq+6NRAjS/GW0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726828720; c=relaxed/simple; bh=PQtI6Eq+0NNZ1EjmJWIF8iif7ccPxNWvibOjFTIuvEQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=dfgnIJCtrUn+iTsNCqEAhYWmWgumXewMODYNn6oJmG/PDQjamX1xKa1RXf3kQOdIdqQrBKBNGZRoG55nPy0RPEt6aiQgq6n/U1x1YBzVuBeHYnBW25UK5lHN6iylIEhLEiZTItz2WaQtcXItgRnGGhAzJEFrYMxntN5ajkuAhwc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Y2cH5o+V; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Y2cH5o+V" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48K8WM9l003191; Fri, 20 Sep 2024 10:38:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= aNqRE66vkY7YNhrJNxX3DY+Qa8VGDefXPcm3WMgGzCQ=; b=Y2cH5o+VVwNHG2fg 1J2aEvsS49LaxgxM7vjfSh8j6TX386jLBDQ7bQPxbB8EeMKtgTKrkIac2pktMDLb nZXIl3qC2iBROumTiRVZHWJftw4xY5eIBvto5teVrtwVA69ejezoV1egx6Bznmts tytF4D/q0Yn7O8DiTMEuJV10rtb7MXy8vrFavbeeas+ry56gIVvQG8ewVW5sJiIq T2PAqnoTuyb7zk4qzy98reupSNknRvzponRkNt8XAm6kW1U+r+juC9ej2LXlEe5+ 1ZwwUAV+OBhug2xGV7dnQu9isUtrFVGqkGHpdi93dncIQWlxLsW+2u/ykElDr/Gr H2W7sw== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41n4hf8p8g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 20 Sep 2024 10:38:35 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48KAcYnW001842 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 20 Sep 2024 10:38:34 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 20 Sep 2024 03:38:30 -0700 From: Taniya Das Date: Fri, 20 Sep 2024 16:08:16 +0530 Subject: [PATCH v2 2/4] clk: qcom: rpmhcc: Add support for QCS615 Clocks Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240920-qcs615-clock-driver-v2-2-2f6de44eb2aa@quicinc.com> References: <20240920-qcs615-clock-driver-v2-0-2f6de44eb2aa@quicinc.com> In-Reply-To: <20240920-qcs615-clock-driver-v2-0-2f6de44eb2aa@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ajit Pandey , Imran Shaik , Jagadeesh Kona CC: , , , , Taniya Das X-Mailer: b4 0.14-dev-f7c49 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: faJ3afgEHkskVgyG1uDSrUEGer6M9ayB X-Proofpoint-GUID: faJ3afgEHkskVgyG1uDSrUEGer6M9ayB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 mlxlogscore=943 adultscore=0 malwarescore=0 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409200076 Add the RPMHCC clocks required for QCS615 SoC. Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-rpmh.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 4acde937114a..01418b1c09b0 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -795,6 +795,24 @@ static const struct clk_rpmh_desc clk_rpmh_x1e80100 = { .num_clks = ARRAY_SIZE(x1e80100_rpmh_clocks), }; +static struct clk_hw *qcs615_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_qcs615 = { + .clks = qcs615_rpmh_clocks, + .num_clks = ARRAY_SIZE(qcs615_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) { @@ -878,6 +896,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) } static const struct of_device_id clk_rpmh_match_table[] = { + { .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615}, { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000}, { .compatible = "qcom,sa8775p-rpmh-clk", .data = &clk_rpmh_sa8775p}, { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180},