| Message ID | 20240923125713.3411487-6-quic_qianyu@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for PCIe3 on x1e80100 | expand |
On Mon, Sep 23, 2024 at 05:57:12AM -0700, Qiang Yu wrote: No need to mention the ops/cfg in subject. It is a detail for patch description. So use: "PCI: qcom: Add support for X1E80100 SoC" Also add some information about the IP capability. Like what speed/gen version it supports, lane width etc... > Currently the ops_1_9_0 which is being used for X1E80100 has config_sid > callback to config BDF to SID table. However, this callback is not > required for X1E80100 because it has smmuv3 support and BDF to SID table > will be not present. > > Hence introduce cfg_1_38_0 and ops_1_38_0 with config_sid callback being > NULL since X1E80100 has IP version 1.38.0. > I'd rewrite the last sentence as below: "Hence add support for X1E80100 by introducing a new ops and cfg structures that don't require the config_sid callback. This could be reused by the future platforms based on SMMUv3." - Mani > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 88a98be930e3..56ba8bc72f78 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 = { > .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > }; > > +/* Qcom IP rev.: 1.38.0 */ > +static const struct qcom_pcie_ops ops_1_38_0 = { > + .get_resources = qcom_pcie_get_resources_2_7_0, > + .init = qcom_pcie_init_2_7_0, > + .post_init = qcom_pcie_post_init_2_7_0, > + .host_post_init = qcom_pcie_host_post_init_2_7_0, > + .deinit = qcom_pcie_deinit_2_7_0, > + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > +}; > + > static const struct qcom_pcie_cfg cfg_1_0_0 = { > .ops = &ops_1_0_0, > }; > @@ -1409,6 +1419,10 @@ static const struct qcom_pcie_cfg cfg_sc8280xp = { > .no_l0s = true, > }; > > +static const struct qcom_pcie_cfg cfg_1_38_0 = { > + .ops = &ops_1_38_0, > +}; > + > static const struct dw_pcie_ops dw_pcie_ops = { > .link_up = qcom_pcie_link_up, > .start_link = qcom_pcie_start_link, > @@ -1837,7 +1851,7 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, > { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, > { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, > - { .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 }, > + { .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_38_0 }, > { } > }; > > -- > 2.34.1 >
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 88a98be930e3..56ba8bc72f78 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 = { .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; +/* Qcom IP rev.: 1.38.0 */ +static const struct qcom_pcie_ops ops_1_38_0 = { + .get_resources = qcom_pcie_get_resources_2_7_0, + .init = qcom_pcie_init_2_7_0, + .post_init = qcom_pcie_post_init_2_7_0, + .host_post_init = qcom_pcie_host_post_init_2_7_0, + .deinit = qcom_pcie_deinit_2_7_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, +}; + static const struct qcom_pcie_cfg cfg_1_0_0 = { .ops = &ops_1_0_0, }; @@ -1409,6 +1419,10 @@ static const struct qcom_pcie_cfg cfg_sc8280xp = { .no_l0s = true, }; +static const struct qcom_pcie_cfg cfg_1_38_0 = { + .ops = &ops_1_38_0, +}; + static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link, @@ -1837,7 +1851,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, - { .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_38_0 }, { } };
Currently the ops_1_9_0 which is being used for X1E80100 has config_sid callback to config BDF to SID table. However, this callback is not required for X1E80100 because it has smmuv3 support and BDF to SID table will be not present. Hence introduce cfg_1_38_0 and ops_1_38_0 with config_sid callback being NULL since X1E80100 has IP version 1.38.0. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> --- drivers/pci/controller/dwc/pcie-qcom.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)