| Message ID | 20240925-fix-postdiv-mask-v2-1-b825048b828b@mainlining.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set | expand |
On Wed, Sep 25, 2024 at 08:33:20PM GMT, Barnabás Czémán wrote: > Many qcom clock drivers do not have .width set. In that case value of > (p)->width - 1 will be negative which breaks clock tree. Fix this > by checking if width is zero, and pass 3 to GENMASK if that's the case. > > Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider") > Fixes: 2c4553e6c485 ("clk: qcom: clk-alpha-pll: Fix the pll post div mask") I think one Fixes tag should be enough. Nevertheless, Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> > --- > Changes in v2: > - Pass 3 to GENMASK instead of 0. > - Add more Fixes tag for reference root cause. > - Link to v1: https://lore.kernel.org/r/20240925-fix-postdiv-mask-v1-1-f70ba55f415e@mainlining.org > --- > drivers/clk/qcom/clk-alpha-pll.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index f9105443d7dbb104e3cb091e59f43df25999f8b3..be9bee6ab65f6e08d5ae764d94a92e395e227fbc 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -40,7 +40,7 @@ #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) # define PLL_POST_DIV_SHIFT 8 -# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) +# define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0) # define PLL_ALPHA_MSB BIT(15) # define PLL_ALPHA_EN BIT(24) # define PLL_ALPHA_MODE BIT(25)
Many qcom clock drivers do not have .width set. In that case value of (p)->width - 1 will be negative which breaks clock tree. Fix this by checking if width is zero, and pass 3 to GENMASK if that's the case. Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider") Fixes: 2c4553e6c485 ("clk: qcom: clk-alpha-pll: Fix the pll post div mask") Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> --- Changes in v2: - Pass 3 to GENMASK instead of 0. - Add more Fixes tag for reference root cause. - Link to v1: https://lore.kernel.org/r/20240925-fix-postdiv-mask-v1-1-f70ba55f415e@mainlining.org --- drivers/clk/qcom/clk-alpha-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- base-commit: 62f92d634458a1e308bb699986b9147a6d670457 change-id: 20240925-fix-postdiv-mask-ba47ecd23ea3 Best regards,