From patchwork Fri Sep 27 10:30:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pablo Sun X-Patchwork-Id: 13814116 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB21E1BC9E6; Fri, 27 Sep 2024 10:31:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727433066; cv=none; b=r9Ng14F/lbPrVrl+qDHmwCQs7xALQ09BHbYoJEFRcUNnrYYBl67oLStCQXlzT3smDWd+ud1UjZ4sUpT1LXxrOf29Z+P6X39HEv0nmOL8E6XLhT+mrcITzw5/3X4i1X6bhYSNNTIxzHHirC6eWRdQGNPuYfcCHKnlo4K4rrKh+Og= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727433066; c=relaxed/simple; bh=3jeHIz3CzfYt0YlG8Xs7c472A5tNrbVjbV6+o2SkaiY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LTjzGEPJGYyfm8/rVddq8zraQm9dvXCFMF1RIgNr8ClFzzfZN8LMwaXUVbTQ9eoP3sJ9WSEA1abbqVTaUqmWoNeuqkgn3sgrFw2bYkc9pes+U445dDYMWcXzsv47XCytDnTVef7egz8SfyJmvQ7dpxJ/nLfO0TZsvcyjRhngN3E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=PV1hMPdh; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="PV1hMPdh" X-UUID: 9474ad207cbb11efb66947d174671e26-20240927 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=BTEB+qw5pfDIJJoYTtxRNkXgNsq9QruJuOS6fxVByGo=; b=PV1hMPdhfcb6d30oi0C12WkjiQStUPzJdWC0LUoRrW2NTFBnIChbTPcwD2DqBrXFm6+q2acFFTvlIhGwJnw7adFi+s9q5XM4ZDQ4bMswm1D9ABwLr9r55d8LVNmCQweOvjS5bLHjLB+CkfL0Ud6Et3O3lJOuQrgLtLTDx3n/rfA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:26c16793-1c0d-473c-8649-54687eedb33a,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6dc6a47,CLOUDID:3438aa9e-8e9a-4ac1-b510-390a86b53c0a,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 9474ad207cbb11efb66947d174671e26-20240927 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 169920955; Fri, 27 Sep 2024 18:30:56 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 27 Sep 2024 03:30:55 -0700 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 27 Sep 2024 18:30:55 +0800 From: Pablo Sun To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd , Srinivas Kandagatla CC: , , , , , Pablo Sun Subject: [PATCH v2 4/6] arm64: dts: mediatek: mt8188: Add efuse for GPU speed binning Date: Fri, 27 Sep 2024 18:30:03 +0800 Message-ID: <20240927103005.17605-5-pablo.sun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240927103005.17605-1-pablo.sun@mediatek.com> References: <20240927103005.17605-1-pablo.sun@mediatek.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N The OPP table of mt8188 GPU contains duplicated frequencies for different speed bins. In order to support OPP table, we need to provide the speed bin info in the efuse data so the GPU driver could properly set the supported hardware speed bin. Signed-off-by: Pablo Sun Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 02a5bb4dbd1f..129edaf33704 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1752,6 +1752,11 @@ efuse: efuse@11f20000 { lvts_efuse_data1: lvts1-calib@1ac { reg = <0x1ac 0x40>; }; + + gpu_speedbin: gpu-speedbin@580 { + reg = <0x581 0x1>; + bits = <0 3>; + }; }; gpu: gpu@13000000 { @@ -1763,6 +1768,8 @@ gpu: gpu@13000000 { , ; interrupt-names = "job", "mmu", "gpu"; + nvmem-cells = <&gpu_speedbin>; + nvmem-cell-names = "speed-bin"; operating-points-v2 = <&gpu_opp_table>; power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>, <&spm MT8188_POWER_DOMAIN_MFG3>,