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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?AzWZovVpso2Z33rW4UNuYxjzmsM7?= =?utf-8?q?GWVgw6VAXIjQ8SoMMORC2sE1p+3QbLWfhxGrY2qSCB+ttMqMivBejti2vtwKWodlj?= =?utf-8?q?++3SxTHgReG2IaotryrLmEwd5v9I561eNNHbNoy8ClOfSViR2YpXlQ+1hwlafUx9P?= =?utf-8?q?lEXgjTtzAUdiuHDVjgFsagJccyO2qa/y5q0HrpwB7+A88ClbWmWoZeIht0i2ZOq+W?= =?utf-8?q?cFavBKAfbzbwseo2qTQ5MpC7fL2OWBmpFe7FZj9gNFzlydQKLJxvci+14eI1JxTZu?= =?utf-8?q?mQck5h4aFjG89qQ7T0Jggq5Uey+tNaROsnhk6mQuiqY81FxXUdEiuse5U6JeuaS8Z?= =?utf-8?q?MA3I3WefY0Iu+jqKFm0gdPh2d8AbJ9nRGBW9c/qPG/TDxVqorh7UDEUdNvRMNULeg?= =?utf-8?q?egO4veAcfKJPnVqYmpvj683HdX4XWFm68vuelxm/6O9G2mlSuRQUONFEcxvfN0ILA?= =?utf-8?q?QvEmfFjyG5y/H+dE3HQM4RnSghpoMncIY5PLea8dRuvW3cNLolhrTsRuXnAexTr16?= =?utf-8?q?dB5+YwhUn0KnXVw1O1Nl4mwGUi0wlIUohWpJsh0Xcag0KEbWmWdq5naCqbi3Xe97z?= =?utf-8?q?HOjzz2/z38t0og/rrzTbYrkFiPOx63dfVX+pz00hLK4EuuugY7uu96PoFMlnVCizl?= =?utf-8?q?ZGK5dIrqk6s4tJwGfcCz0F4Z3crRarBfDb2uaMwy/unZLGRIStXjgVyAdCYz5UmKh?= =?utf-8?q?zsOz7t5WIOlKo5jh0PK1jzI3xdTTLjTJfoOb0WiXO8upYnlU5xpM65ztJilQi+GP2?= =?utf-8?q?vXBwWLuO2onKnjvUWiDCSqbyYAgO0T/J/4mlMSfks08B9eZkdLxgsbNOEshod+msI?= =?utf-8?q?zAVOK6JG26lF0DzCOjmPz6jKELNQjBgwQZ5w7SCVugsuJdOIboeJgLHfviQ+byNXi?= =?utf-8?q?pFPPwc0zJSVAQX0uKDIAdyPjiVrQ60EFPZI99A73n2fJhzuYJ9iPzS9Cs+Yinix17?= =?utf-8?q?9+OsLoGedhVe7T5g+GdE8UNYAZ1PfKgXEWIWX69j7uUT19GyahhdOxL0/vw3dxQjs?= =?utf-8?q?IEg8aoYIyW18B6A1xfMnjC7hbjpDjrMvBSv9nvYL2dNrIwl9ludKex+90oo7Enpdc?= =?utf-8?q?zFTEIOYSNa9hKB5Miqv0a3tKsKYQ6HNbdwlTakuk3z7QmH2bi/GKyTu2mfXDC7Tzm?= =?utf-8?q?MNTnkbW+u0BNqs4FOEB0cPWMt1HRvLkp7WstAWbVyoNiXSiFB0O4dQizyrc5IEreg?= =?utf-8?q?AtTB1upvzKu1sIYEoKWkgoJeJIe3lBAe7SyPV5bExrvOHUFzBEbtkfat0SVsyQ0vA?= =?utf-8?q?lVX8rwIiIbMQbd82uiAqywTglzIbtGibnpTRdpYU2rvG3vwQYoRXNhPZEijS1dV/c?= =?utf-8?q?HtcpMNERwo/GUBpLxz87fj4zNLiLMsYIaBXOIdiOKWX6wC4VERNj86MPcIOM6Nv62?= =?utf-8?q?yp+dm4LZRIM9GP+LQ1+C3zUjgeLSoRwliGMnARvLYZHeyCONwoyGGMRxaxRjUnU6k?= =?utf-8?q?7S2gVucZHenBXF2IoB9SwMfAiv23F7TnvHIzMOmreWnwbnmuMvEF4LYEY6CT6miPp?= =?utf-8?q?4FyZdJMrW2RP?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 42597541-d9ad-4d82-ebf1-08dcec2efa48 X-MS-Exchange-CrossTenant-AuthSource: DB9PR04MB8461.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Oct 2024 09:02:49.2906 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Fiz9BBZG2yLBfYeTAg9Xr7u2aH7G1kRfxWfgrBG6VgchT48fz6r3R+EmKjfma01m6u9YFqPbmYSBo+OTgCD9Fw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8765 From: Peng Fan Back-to-back LPCG writes can be ignored by the LPCG register due to a HW bug. The writes need to be separated by at least 4 cycles of the gated clock. The workaround is implemented as follows: 1. For clocks running greater than or equal to 24MHz, a read followed by the write will provide sufficient delay. 2. For clocks running below 24MHz, add a delay of 4 clock cylces after the write to the LPCG register. Fixes: 2f77296d3df9 ("clk: imx: add lpcg clock support") Signed-off-by: Peng Fan --- drivers/clk/imx/clk-lpcg-scu.c | 34 ++++++++++++++++++++++++++++++---- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-scu.c index dd5abd09f3e206a5073767561b517d5b3320b28c..2cffec0c42dccc256e8dc5e9181952e250870a76 100644 --- a/drivers/clk/imx/clk-lpcg-scu.c +++ b/drivers/clk/imx/clk-lpcg-scu.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -41,6 +42,31 @@ struct clk_lpcg_scu { #define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw) +/* e10858 -LPCG clock gating register synchronization errata */ +static void lpcg_e10858_writel(ulong rate, void __iomem *reg, u32 val) +{ + u32 reg1; + + writel(val, reg); + + if (rate >= 24000000 || rate == 0) { + /* + * The time taken to access the LPCG registers from the AP core + * through the interconnect is longer than the minimum delay + * of 4 clock cycles required by the errata. + * Adding a readl will provide sufficient delay to prevent + * back-to-back writes. + */ + reg1 = readl(reg); + } else { + /* + * For clocks running below 24MHz, wait a minimum of + * 4 clock cycles. + */ + ndelay(4 * (DIV_ROUND_UP(1000000000, rate))); + } +} + static int clk_lpcg_scu_enable(struct clk_hw *hw) { struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); @@ -57,7 +83,8 @@ static int clk_lpcg_scu_enable(struct clk_hw *hw) val |= CLK_GATE_SCU_LPCG_HW_SEL; reg |= val << clk->bit_idx; - writel(reg, clk->reg); + + lpcg_e10858_writel(clk_hw_get_rate(hw), clk->reg, reg); spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); @@ -74,7 +101,7 @@ static void clk_lpcg_scu_disable(struct clk_hw *hw) reg = readl_relaxed(clk->reg); reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); - writel(reg, clk->reg); + lpcg_e10858_writel(clk_hw_get_rate(hw), clk->reg, reg); spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); } @@ -149,9 +176,8 @@ static int __maybe_unused imx_clk_lpcg_scu_resume(struct device *dev) * FIXME: Sometimes writes don't work unless the CPU issues * them twice */ - - writel(clk->state, clk->reg); writel(clk->state, clk->reg); + lpcg_e10858_writel(0, clk->reg, clk->state); dev_dbg(dev, "restore lpcg state 0x%x\n", clk->state); return 0;