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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53a00007078sm821563e87.212.2024.10.17.09.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2024 09:57:16 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 17 Oct 2024 19:56:57 +0300 Subject: [PATCH 07/14] clk: qcom: clk-branch: Add support for SREG branch ops Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241017-sar2130p-clocks-v1-7-f75e740f0a8d@linaro.org> References: <20241017-sar2130p-clocks-v1-0-f75e740f0a8d@linaro.org> In-Reply-To: <20241017-sar2130p-clocks-v1-0-f75e740f0a8d@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Neil Armstrong , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kalpak Kawadkar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2868; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=lk5Jzsxf7Q9DWyX31WiRZKJBTl6ko04MqIlsJap0u5w=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnEUHbBZPdRgefZdHDDT5GfTwUsmLMj9DYGrvuj 4JJYFnfOtaJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxFB2wAKCRAU23LtvoBl uJvLD/41ycyKcCJzBRuYDx7+AZNHXyvhVcbB6+X99Ny43LGteSj8H9z9c8SVkOL6ZziSmGXq7tW HmpipYEwHdwUH+2tKUro7XoEwfLDN/DzTVnBr5FQmWdwH/+FPMUwVHK1xsMXtjCDam0Vhmm2i76 VJw7rCU2HfruUuxBKuUg24TpEPxHX0KelUtDxozr98odKOhHW454zNWlmMAgp26RMVoRh93+zHw snxEFxaE4xV4P2MVwwX9XZmThwxZgocUxxupDx3EV+Fey8+iH0sJcJxDHuw/xvR8DmWJDte8I2S Dw+po1Od9c06k5KxPSLkF+LSNc9//gtzzxOI9pd2nDwZncmvGkmQQ0hY9WAXyEf8WdQ5I9epUg5 CORLDZ1A6pGS3F5DTw5+xG1e9w8O7bfY3h05cE2uzz97eL+73MmTLOYl9bWBavNlJKhYROZsc2z jKhEbtUpfK+Zg4CjIeVOUd+juoGq9vH377vCqN0GqgTWVwlqfE+NXmQ+5GcT9LeWta6hd8P5yHW 46hV98zIOA5zcqfViQB94LPx4YOpwZ+Kn2K4b6tk88FrU8mKBGxVHwcqGgb9JQc0QOqGGJ6PC1+ V6WZnsww6S15D1jJEboMq93JvWLEJL7HKsSqNeXa4/CW4sz6YiUFDAmOThaPyQ3WNzRgj5UI5S1 luye7dxSMGDvhmw== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A From: Kalpak Kawadkar Add support for SREG branch ops. This is for the clocks which require additional register operations with the SREG register as a part of enable / disable operations. Signed-off-by: Kalpak Kawadkar Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-branch.c | 32 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-branch.h | 4 ++++ 2 files changed, 36 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index c4c7bd565cc9a3926e24bb12ed6355ec6ddd19fb..9142a33b6b3ba72a7dd9ff80a64c17f2a1746e8c 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -170,6 +170,31 @@ static void clk_branch2_mem_disable(struct clk_hw *hw) return clk_branch2_disable(hw); } +static int clk_branch2_sreg_enable(struct clk_hw *hw) +{ + struct clk_branch *br = to_clk_branch(hw); + u32 val; + int ret; + + ret = clk_enable_regmap(hw); + if (ret) + return -EINVAL; + + return regmap_read_poll_timeout(br->clkr.regmap, br->sreg_enable_reg, + val, !(val & br->sreg_core_ack_bit), 1, 200); +} + +static void clk_branch2_sreg_disable(struct clk_hw *hw) +{ + struct clk_branch *br = to_clk_branch(hw); + u32 val; + + clk_disable_regmap(hw); + + regmap_read_poll_timeout(br->clkr.regmap, br->sreg_enable_reg, + val, val & br->sreg_periph_ack_bit, 1, 200); +} + const struct clk_ops clk_branch2_mem_ops = { .enable = clk_branch2_mem_enable, .disable = clk_branch2_mem_disable, @@ -203,3 +228,10 @@ const struct clk_ops clk_branch2_prepare_ops = { .is_prepared = clk_is_enabled_regmap, }; EXPORT_SYMBOL_GPL(clk_branch2_prepare_ops); + +const struct clk_ops clk_branch2_sreg_ops = { + .enable = clk_branch2_sreg_enable, + .disable = clk_branch2_sreg_disable, + .is_enabled = clk_is_enabled_regmap, +}; +EXPORT_SYMBOL(clk_branch2_sreg_ops); diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 47bf59a671c3c8516a57c283fce548a6e5f16619..149d04bae25d1a54999e0f938c4fce175a7c3e42 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -24,8 +24,11 @@ struct clk_branch { u32 hwcg_reg; u32 halt_reg; + u32 sreg_enable_reg; u8 hwcg_bit; u8 halt_bit; + u32 sreg_core_ack_bit; + u32 sreg_periph_ack_bit; u8 halt_check; #define BRANCH_VOTED BIT(7) /* Delay on disable */ #define BRANCH_HALT 0 /* pol: 1 = halt */ @@ -111,6 +114,7 @@ extern const struct clk_ops clk_branch_simple_ops; extern const struct clk_ops clk_branch2_aon_ops; extern const struct clk_ops clk_branch2_mem_ops; extern const struct clk_ops clk_branch2_prepare_ops; +extern const struct clk_ops clk_branch2_sreg_ops; #define to_clk_branch(_hw) \ container_of(to_clk_regmap(_hw), struct clk_branch, clkr)