| Message ID | 20241017030412.265000-4-quic_qianyu@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add support for PCIe3 on x1e80100 | expand |
On Wed, Oct 16, 2024 at 08:04:08PM -0700, Qiang Yu wrote: > Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt > to the host CPU. This interrupt can be used by the device driver to handle > PCIe link specific events such as Link up and Link down, which give the > driver a chance to start bus enumeration on its own when link is up and > initiate link training if link goes to a bad state. The PCIe driver can > still work without this interrupt but it will provide a nice user > experience when device gets plugged and removed. > > Hence, document it in the binding along with the existing MSI interrupts. > Global interrupt is parsed as optional in driver, so adding it in bindings > will not break the ABI. > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > --- > .../devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml index a9db0a231563..257068a18264 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml @@ -47,9 +47,10 @@ properties: interrupts: minItems: 8 - maxItems: 8 + maxItems: 9 interrupt-names: + minItems: 8 items: - const: msi0 - const: msi1 @@ -59,6 +60,7 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global resets: minItems: 1 @@ -130,9 +132,10 @@ examples: <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPU. This interrupt can be used by the device driver to handle PCIe link specific events such as Link up and Link down, which give the driver a chance to start bus enumeration on its own when link is up and initiate link training if link goes to a bad state. The PCIe driver can still work without this interrupt but it will provide a nice user experience when device gets plugged and removed. Hence, document it in the binding along with the existing MSI interrupts. Global interrupt is parsed as optional in driver, so adding it in bindings will not break the ABI. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> --- .../devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)