| Message ID | 20241023-axi-clkgen-fix-axiclk-v1-1-980a42ba51c3@analog.com (mailing list archive) |
|---|---|
| State | Under Review |
| Headers | show |
| Series | clk: clk-axi-clkgen: make sure to enable the AXI bus clock | expand |
On Wed, Oct 23, 2024 at 04:56:54PM +0200, Nuno Sa wrote: > In order to access the registers of the HW, we need to make sure that > the AXI bus clock is enabled. Hence let's increase the number of clocks > by one. > > In order to keep backward compatibility, the new axi clock must be the > last phandle in the array. To make the intent clear, a non mandatory > clock-names property is also being added. Hmm, I'm not sure. I think clock-names actually may need to be mandatory here, as otherwise you'll not what the second clock is. The driver would have to interpret no clock-names meaning clock 2 was clkin2. > > Fixes: 0e646c52cf0e ("clk: Add axi-clkgen driver") > Signed-off-by: Nuno Sa <nuno.sa@analog.com> > --- > .../devicetree/bindings/clock/adi,axi-clkgen.yaml | 21 +++++++++++++++++---- > 1 file changed, 17 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml > index 5e942bccf27787d7029f76fc1a284232fb7f279d..f5f80e61c119b8a68cb6e7a26ed275764f8d200f 100644 > --- a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml > +++ b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml > @@ -26,9 +26,21 @@ properties: > description: > Specifies the reference clock(s) from which the output frequency is > derived. This must either reference one clock if only the first clock > - input is connected or two if both clock inputs are connected. > - minItems: 1 > - maxItems: 2 > + input is connected or two if both clock inputs are connected. The last > + clock is the AXI bus clock that needs to be enabled so we can access the > + core registers. > + minItems: 2 > + maxItems: 3 > + > + clock-names: > + oneOf: > + - items: > + - const: clkin1 > + - const: s_axi_aclk > + - items: > + - const: clkin1 > + - const: clkin2 > + - const: s_axi_aclk > > '#clock-cells': > const: 0 > @@ -50,5 +62,6 @@ examples: > compatible = "adi,axi-clkgen-2.00.a"; > #clock-cells = <0>; > reg = <0xff000000 0x1000>; > - clocks = <&osc 1>; > + clocks = <&osc 1>, <&clkc 15>; > + clock-names = "clkin1", "s_axi_aclk"; > }; > > -- > 2.47.0 >
diff --git a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml index 5e942bccf27787d7029f76fc1a284232fb7f279d..f5f80e61c119b8a68cb6e7a26ed275764f8d200f 100644 --- a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml +++ b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml @@ -26,9 +26,21 @@ properties: description: Specifies the reference clock(s) from which the output frequency is derived. This must either reference one clock if only the first clock - input is connected or two if both clock inputs are connected. - minItems: 1 - maxItems: 2 + input is connected or two if both clock inputs are connected. The last + clock is the AXI bus clock that needs to be enabled so we can access the + core registers. + minItems: 2 + maxItems: 3 + + clock-names: + oneOf: + - items: + - const: clkin1 + - const: s_axi_aclk + - items: + - const: clkin1 + - const: clkin2 + - const: s_axi_aclk '#clock-cells': const: 0 @@ -50,5 +62,6 @@ examples: compatible = "adi,axi-clkgen-2.00.a"; #clock-cells = <0>; reg = <0xff000000 0x1000>; - clocks = <&osc 1>; + clocks = <&osc 1>, <&clkc 15>; + clock-names = "clkin1", "s_axi_aclk"; };
In order to access the registers of the HW, we need to make sure that the AXI bus clock is enabled. Hence let's increase the number of clocks by one. In order to keep backward compatibility, the new axi clock must be the last phandle in the array. To make the intent clear, a non mandatory clock-names property is also being added. Fixes: 0e646c52cf0e ("clk: Add axi-clkgen driver") Signed-off-by: Nuno Sa <nuno.sa@analog.com> --- .../devicetree/bindings/clock/adi,axi-clkgen.yaml | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-)