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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e10a915sm209542e87.12.2024.10.25.08.04.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 08:04:07 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 25 Oct 2024 18:03:41 +0300 Subject: [PATCH v3 07/11] clk: qcom: rpmh: add support for SAR2130P Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241025-sar2130p-clocks-v3-7-48f1842fd156@linaro.org> References: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> In-Reply-To: <20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Neil Armstrong , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1793; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=L1rjSA7hLRyjlIeLPYAhbgLNuAgpRygH7wmtCWHxdlw=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnG7NUk3yWZdzVjPwVQa1LUVgaj+sDlUPqXdKm0 6q66y76nnWJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZxuzVAAKCRAU23LtvoBl uHmJEAC4U2gI4CvDeOJh7p/G2E3CyEJ6aT08SK/0Zud8/VQL6zEyXSEWFNbsNfEg2SaIeuChzce k3sRpy6BMKi/VULdMt5eT2C3e38FH5tcZeVyGpLii41BP3uoQnJSABuXKTEiyRb3b8yaB0fK7m7 99LEjfJEFfZB+f9A/pdSEXq+i5bsEFFkk8QcxZT3R3NzhWbDY4aNEBmvgXSPwgs116baWtZQWGg ON2ppeY8pgF+aPFy01U2Q8cfg4mhOLMhRlptbSHE1j80okXJ9A5t3MI79j4BHfG49KOWWub1IhE DWfOVt7ToMLNf3zyA0y2R5RtWjAezFMLLuCdDQX1Dd5SVs0c6jVGY8ybLw0s0eoj+P8tzFMmMEn 2oLCXsgDOAhPshVdU7gsgeJC4kAFakL4F7P2SADf60IsztOSoDzyj3cQNodshFWFK7oljZQfKWX bJFgCH97c48lNpvj2rRpvDYL1cQwdx5AZeW8enfjIAxXt4Ghi9fPtq1D0qjv54r/uk2S2uWpgpk cZgNk8FNGWXMH532pxg8nS0Gw5abGolKv5A37M9nE5otR/cW+XUcwXOSsHGSFrARz6WJLmkCdyj XgyDezZKMJRI5Avqe5OW2OJWyjfeGHXxgZNEji0V6DB0sDHFEmBdixrMGzPm4dzejw1hSLG6YWP AVTyDazzWU2KwVA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Define clocks as supported by the RPMh on the SAR2130P platform. It seems that on this platform RPMh models only CXO clock. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-rpmh.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 4acde937114af3d7fdc15f3d125a72d42d0fde21..eefc322ce367989f625f1285dcccddbdd8341a12 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -389,6 +389,18 @@ DEFINE_CLK_RPMH_BCM(ipa, "IP0"); DEFINE_CLK_RPMH_BCM(pka, "PKA0"); DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0"); +static struct clk_hw *sar2130p_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sar2130p = { + .clks = sar2130p_rpmh_clocks, + .num_clks = ARRAY_SIZE(sar2130p_rpmh_clocks), +}; + static struct clk_hw *sdm845_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, @@ -880,6 +892,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000}, { .compatible = "qcom,sa8775p-rpmh-clk", .data = &clk_rpmh_sa8775p}, + { .compatible = "qcom,sar2130p-rpmh-clk", .data = &clk_rpmh_sar2130p}, { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180}, { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, { .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp},