@@ -51,6 +51,9 @@ static int meson_clk_phase_set_phase(struct clk_hw *hw, int degrees)
struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
unsigned int val;
+ if (phase->ph.width > 8)
+ return -EINVAL;
+
val = meson_clk_degrees_to_val(degrees, phase->ph.width);
meson_parm_write(clk->map, &phase->ph, val);
@@ -110,6 +113,9 @@ static int meson_clk_triphase_set_phase(struct clk_hw *hw, int degrees)
struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
unsigned int val;
+ if (tph->ph0.width > 8)
+ return -EINVAL;
+
val = meson_clk_degrees_to_val(degrees, tph->ph0.width);
meson_parm_write(clk->map, &tph->ph0, val);
meson_parm_write(clk->map, &tph->ph1, val);
@@ -167,6 +173,9 @@ static int meson_sclk_ws_inv_set_phase(struct clk_hw *hw, int degrees)
struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk);
unsigned int val;
+ if (tph->ph.width > 8)
+ return -EINVAL;
+
val = meson_clk_degrees_to_val(degrees, tph->ph.width);
meson_parm_write(clk->map, &tph->ph, val);
meson_parm_write(clk->map, &tph->ws, val ? 0 : 1);
In the meson_clk_phase_set_phase() function, the variable phase->ph.width is of type u8, with a range of 0 to 255. When calling meson_clk_degrees_to_val with width as an argument, if width > 8, phase_step(width) will return 0. Lead to a division by zero error in DIV_ROUND_CLOSEST(). The same issue exists in the meson_clk_triphase_set_phase() and meson_sclk_ws_inv_set_phase(). Fixes: 7b70689b07c1 ("clk: meson: add sclk-ws driver") Cc: <stable@vger.kernel.org> Signed-off-by: Zicheng Qu <quzicheng@huawei.com> --- drivers/clk/meson/clk-phase.c | 9 +++++++++ 1 file changed, 9 insertions(+)