From patchwork Mon Oct 28 14:04:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 13853509 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FC0D1DDC3F; Mon, 28 Oct 2024 14:04:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730124298; cv=none; b=d5e9G/blNvuefdMHHUBEmdht5nEKtY4cj48XJJ58Tqvv0jYiJfnnTpcEz8V7Yh4lca9UtcpDGgIx4tAmmlLDaVsNKnpj4NAnajU+EtFfqm6zPAOFU3x0cuNxeHitpi0BxSm9GM0jJiWL6RxYpSQ8qWuCxfZR/7XBjlYwItKZ4aA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730124298; c=relaxed/simple; bh=Tg6LNppTIuWtA+krGH0NCUp5FPo/KCQV5VDmFVSFNi4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=SJfbVIxbN/F3tYEudQ7EUvG6sxFNrOFfyP0lSUEtE8FZ0ptVw+NVuCCFG8Hg8h7tPhmAC+xEMJFN4U3HPTKpHcMv8iZ8BfTV0ENU7wMiT3h0exCAxLiRKw4bGOKms570PqXQvuc0NBL4+af7+oRlWPXOLFmctSDnDyThF3fldl8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=hHsoMopL; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="hHsoMopL" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49SBEr16017467; Mon, 28 Oct 2024 14:04:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= c0PGrjCxNUo45tfZBFnlE48NBdI+gT1LxukW9yIcNd8=; b=hHsoMopLkhB8qVla WGpeHHeJeMXhZYizVN3WAKFYhhJiBOUdZqXuRHVa21c/mcvMoUH2KKKDnG4Foycb wGSizCAvl7Kq2RGVXG5+7wXzpL7L1bT9hG4Q6Na1Lm0cFYy07/w3YIfcn/DbTTM2 EsyiQldWH+chqVN9NBPMU/9k8xH2Vfr5FdbBuEoqOuUc5XaPQgrlxL22pILx0iZS cqDiUUFHz4eCWODknBEplL95RfA0Ir8kamqHXBDIAJSNt+QJSXSGfpXIZzA+F6Rl jd+9s92lq1SoKS+yk/KYJxEFysJN9aaw/wid2qNTR+BIUSTdPupN5ux5l/PszjcB MTFvcw== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42gqrgn6jr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 14:04:45 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49SE4iV3031135 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 14:04:44 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Oct 2024 07:04:39 -0700 From: Luo Jie Date: Mon, 28 Oct 2024 22:04:11 +0800 Subject: [PATCH v5 4/4] arm64: dts: qcom: Add CMN PLL node for IPQ9574 SoC Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241028-qcom_ipq_cmnpll-v5-4-339994b0388d@quicinc.com> References: <20241028-qcom_ipq_cmnpll-v5-0-339994b0388d@quicinc.com> In-Reply-To: <20241028-qcom_ipq_cmnpll-v5-0-339994b0388d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730124258; l=3979; i=quic_luoj@quicinc.com; s=20240808; h=from:subject:message-id; bh=Tg6LNppTIuWtA+krGH0NCUp5FPo/KCQV5VDmFVSFNi4=; b=bmqGUrfXGFR4/akAPgt/Bx6poRlc2COUcwcpaY38jHmGkzpkPtxivM2sCQg8qe7FjKaeEhV1b v6GriMb4KlCC/qsEE6X4uDtnCghIatuJ4YIXSWGFl/O79sqF9Ew7QRf X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=P81jeEL23FcOkZtXZXeDDiPwIwgAHVZFASJV12w3U6w= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: JI-Z65EWI7ySiN8V0I4pvT9v2QQ0QyiM X-Proofpoint-GUID: JI-Z65EWI7ySiN8V0I4pvT9v2QQ0QyiM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 clxscore=1015 impostorscore=0 suspectscore=0 spamscore=0 mlxscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280113 The CMN PLL clock controller allows selection of an input clock rate from a defined set of input clock rates. It in-turn supplies fixed rate output clocks to the hardware blocks that provide the ethernet functions such as PPE (Packet Process Engine) and connected switch or PHY, and to GCC. The reference clock of CMN PLL is routed from XO to the CMN PLL through the internal WiFi block. .XO (48 MHZ or 96 MHZ)-->WiFi (multiplier/divider)-->48 MHZ to CMN PLL. The reference input clock from WiFi to CMN PLL is fully controlled by the bootstrap pins which select the XO frequency (48 MHZ or 96 MHZ). Based on this frequency, the divider in the internal Wi-Fi block is automatically configured by hardware (1 for 48 MHZ, 2 for 96 MHZ), to ensure output clock to CMN PLL is 48 MHZ. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 16 ++++++++++++++- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 26 +++++++++++++++++++++++- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi index 91e104b0f865..f026c2a9d0c0 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -3,7 +3,7 @@ * IPQ9574 RDP board common device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -164,6 +164,20 @@ &usb3 { status = "okay"; }; +/* + * The bootstrap pins for the board select the XO clock frequency, + * which automatically enables the right dividers to ensure the + * reference clock output to CMNPLL is 48 MHZ. + */ +&cmn_pll_ref_clk { + clock-div = <1>; + clock-mult = <1>; +}; + &xo_board_clk { clock-frequency = <24000000>; }; + +&xo_clk { + clock-frequency = <48000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 14c7b3a78442..ad9cdb1f76db 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -3,10 +3,11 @@ * IPQ9574 SoC device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include +#include #include #include #include @@ -19,6 +20,12 @@ / { #size-cells = <2>; clocks { + cmn_pll_ref_clk: cmn-pll-ref-clk { + compatible = "fixed-factor-clock"; + clocks = <&xo_clk>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -28,6 +35,11 @@ xo_board_clk: xo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; + + xo_clk: xo-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; }; cpus { @@ -243,6 +255,18 @@ mdio: mdio@90000 { status = "disabled"; }; + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq9574-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&cmn_pll_ref_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", "ahb", "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <12000000000>; + }; + qfprom: efuse@a4000 { compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; reg = <0x000a4000 0x5a1>;